Showing papers presented at "Asia Symposium on Quality Electronic Design in 2013"

On testing of MEDA based digital microfluidics biochips

Abstract: Recent years have seen rapid progress in using digital microfluidics based biochips for biomedical assays The testing and reliability of these biochips is crucial when they are used in point-of-care diagnostics applications As the scalability and complexity of biomedical assays increases, there is a need for efficient testing methodologies to ensure reliability of these biochips The conventional testing methodologies will not be sufficient for the recently proposed and highly scalable Micro-electrode-dot array (MEDA) architecture based digital microfluidics This is because of the advanced fluidic movement operations incorporated in the MEDA architecture This paper investigates the testing methodologies for conventional digital microfluidics based biochips and their relevancy to the MEDA architecture based digital microfluidics biochips

Applications of crystalline Indium-Gallium-Zinc-Oxide technology to LSI: Memory, processor, image sensor, and field programmable gate array

Abstract: Crystalline In-Ga-Zn Oxide (IGZO) including c-axis aligned crystal (CAAC) enables FETs to show high reliability and extremely low off-state current. CAAC-IGZO technology is expected to grow to main technology of next-generation displays and is already contributing to mass-production of liquid crystal displays. In this paper by focusing on a very important feature of CAAC-IGZO FET, extremely low off-state current, its pioneering various applications to LSI are reviewed and discussed. In particular, a success in development of a hybrid process of CMOS FETs and CAAC-IGZO FETs promotes our developments of novel memories, processors, image sensors, and recently, field programmable gate arrays (FPGA).

An ABCD parameter-based modeling and analysis of crosstalk induced effects in single-walled carbon nanotube bundle interconnects

Abstract: Single-walled carbon nanotubes (SWCNTs) have the potential to revolutionize the interconnects in future nanoscale integrated circuits. In the proposed work, crosstalk effects are investigated in SWCNTs at 21 nm and 15 nm technology nodes for intermediate as well as global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse as well as dense SWCNT bundled interconnect system. It is evident from the simulation results that the proposed model is not only 100% accurate but also almost 10 times faster than SPICE. The worst case crosstalk induced delay and peak crosstalk noise voltages for SWCNT bundle interconnects are compared to those of conventional copper (Cu) interconnects at the intermediate as well as global level interconnects. Simulation results also confirm that dense SWCNTs are always ahead of sparse SWCNTs with respect to performance advantage numbers over copper for every levels of interconnects and irrespective of technology nodes. As far as the worst case peak crosstalk noise is concerned, there is a critical length after which the performance of the dense SWCNT bundles is better than that of its sparse counterpart. Proposed model, analysis, along with supportive simulation results prove that dense SWCNT bundled interconnect is one of the most promising alterative interconnect solution for future generation of nanoscale circuits compared to copper with respect to performance as well as signal integrity issues.

A low power oscillator based temperature sensor for RFID applications

Abstract: In this paper we present a temperature sensor based on a ring oscillator The ring oscillator uses the CMOS thyristor delay element and has an extremely low power consumption of about 47nW at room temperature with a supply of 05V Low power operation is achieved by eliminating the use of power hungry analog to digital converters (ADCs) at the sensor output As shown the frequency increases linearly with temperature The error in temperature sensing is around -18°C / +1°C with a resolution of 03°C Simulation is carried out with Chartered Semiconductor's 018μm technology Owing to the extremely low power consumption, integration with a radio-frequency identification (RFID) tag is also possible

Thermal simulation analysis of high power LED system using two-resistor compact LED model

Abstract: This paper presents the thermal analysis and validation of high power LED system with simulation and experimental methods. A 3W high power LED package is mounted on MCPCB and heat sink, which is tested inside a (300 × 300 × 300mm) still air chamber with three different forward currents. Experimental measurement with Thermal Transient Tester (T3Ster) is performed to capture the thermal transient characteristic of the LED system. The simulation is conducted with FloEFD 12.1 CFD software, using two-resistor model the LED package is defined with thermal resistance at different forward current. From the validation the simulation result closely match the experimental result, with highest percentage error at 4.75%. The surrounding air temperature of the system is also studied in the simulation. Following the verification, LED system with and without rectangular fixture are simulated and compared. The model without fixture shows better thermal results. The flow trajectory plot shows the difference in air convection with and without fixture. The simulation shows fixture disrupts the natural convection in the chamber.

A possibility of crystalline Indium-Gallium-Zinc-Oxide

Abstract: Crystalline IGZO thin films were first used in consumer products successfully by a joint development with Sharp Corporation. The crystalline IGZO thin films have a CAAC (C-axis Aligned Crystal) structure, a novel crystalline structure without clear grain boundaries. We examined the mechanism of formation of the structure on a given surface and fabricated TFTs using CAAC-IGZO. We examined their characteristics and found that the TFTs had little variation in characteristic and high reliability even with a short channel length L. Application of CAAC-IGZO to various LSIs is expected.

Influence of phosphor packaging configurations on the optical performance of Chip on Board phosphor converted Warm White LEDs

Abstract: The optical properties of high power Warm-White Light Emitting Diodes (WW-LEDs) in Chip-on-Board (COB) package of Dam-and-Fill encapsulation with three different phosphor packaging configurations were investigated in this paper. The phosphor configurations studied were remote phosphor, double phosphor layers and normal phosphor configuration. Analysis of experimental data shows that LED samples in COB package with normal phosphor configuration had the highest efficiency compared to the other two phosphor configurations, differing from usual results obtained in other comparison studies of phosphor configurations in LED packages. This investigation also shows that LED samples with remote phosphor configuration has the highest relative intensity at red-yellow emission region, while LED samples with normal phosphor configuration has the highest relative intensity at blue emission region.

Highly robust and sensitive charge transfer sense amplifier for ultra-low voltage DRAMs

Abstract: A new charge transfer sense amplifier for low voltage DRAMs is proposed. The proposed charge transfer sense amplifier has two features. One is the double boosting sensing node structure, and the other is the dynamic presensing latch. The double boosting sensing node structure consists of two boosting capacitors. The 1st and 2nd boosting capacitors are placed at the boosting nodes and sensing nodes, respectively. The sensing node and boosting node are connected by a PMOS diode-connected transistor. This structure is efficient in achieving high sensitivity in ultra-low supply voltage conditions. The dynamic presensing latch is placed at the sensing nodes between the bit-line pair. The sensing node voltage difference (ΔVSA) develops by the operation of the dynamic presensing latch. Pull-down/up latch works effectively because ΔVSA is larger than bit-line voltage difference. With a 0.5V power supply voltage using a NCSU 45nm process, the proposed charge transfer sense amplifier brings a significant increase of about 3.89 times in ΔVSA and a decrease of 22.3% in the sensing delay time compared with the characteristics obtained by the best-known prior scheme.

Repairing of faulty TSVs using available number of multiplexers in 3D ICs

Abstract: Through-silicon via (TSV) based 3D integrated circuit (IC) testing is promising area to the researchers in modern day semiconductor industry. The manufacturing of 3D ICs may produce TSV defects which reduce yield. Recent work has proposed grouping of functional and redundant TSVs such that the faulty functional TSVs are supported by redundant TSVs and multiplexers (MUXs) are used to implement that group. This paper proposes grouping of functional and redundant TSVs such that a functional TSV is supported by redundant TSVs of other groups. We have presented an algorithm that finds the best grouping of functional and redundant TSVs such that maximum recovery of functional TSVs can be achieved with a given number of MUXs.

Implementation of a physical unclonable function (PUF) with transmission line crosstalk in a chip

Abstract: A physically unclonable function (PUF) is a promising technology that provides the ability to identify network components. Conventional PUF circuitry suffers from a reliability problem in which a consistent output value is not guaranteed because of environmental changes such as the power supply voltage and operating temperature. This paper introduces a PUF circuit that yields consistent responses that overcome fluctuations in the operating conditions. The proposed PUF is based on the variation in the crosstalk between adjacent transmission lines, which reflects the random physical structure of interconnected lines. The proposed PUF cell comprises three transmission lines and a sense amplifier. The sense amplifier catches the crosstalk differences between two adjacent transmission lines. The crosstalk differences reflect a physical structure variation, which is immune to changes in the operating environment. The proposed PUF circuit yields a well-balanced distribution probability, (100/2n)%, for each challenge bit with σ = 1%. The identification generated by the PUF can be regarded as core functionality for authentication and encryption in security applications.

Congestion-oriented approach in placement for analog and mixed-signal circuits

Abstract: Placement design is an essential step in VLSI design and the interaction between different modules makes it a complex process, especially for the integration of analog and mixed-signal circuits. The satisfactory placements of these circuits can be achieved by considering a series of constraints such as symmetry, and general placement constraints-alignment, abutment, preplace, boundary, range and maximum separation. Additionally, the placement result determines the routability of the subsequent routing work. Hence, routability is another important issue that should be considered during the placement phase. In this paper, we propose a new approach which expands the size of certain modules by analyzing the net congestion probability in respect of routability and satisfying the mentioned constraints during the placement process for analog and mixed-signal circuits. Experimental results demonstrate the effectiveness and feasibility of our approach in solving the routability-driven placement problem.

A robust and energy efficient pulse generator for ultra-wide voltage range operations

Abstract: In this paper, a robust and energy efficient pulse generator (PG), dedicated to pulse-triggered flip-flops (pulsed-FFs) in ultra-wide voltage range (UWVR) applications, is proposed. Pulsed-FFs are promising candidate for high-speed and low-power applications, thanks to their small data-to-output delay and their shareable PG. However, UWVR circuits work most of the time under the threshold voltage, where local variations lead to a huge spread in logic delays. Therefore, the designers have to ensure that the minimum width of the pulse signal activating the pulsed-FF is large enough to guarantee the correct functionality of the FF. On the other hand, a too large pulse window would lead to an increase of the hold time, and thus energy overhead for inserting delay buffers, which is not acceptable in energy-efficient circuits. This work presents a pulse generator exhibiting excellent performances in the three figures of merit of PGs. Postlayout simulations showed that, for a small area penalty, the robustness of the pulsed-FF is greatly improved.

Computationally efficient methodology for statistical characterization and yield estimation due to inter- and intra-die process variations

Abstract: In this paper, first we have demonstrated the suitability of Plackett-Burman Design of Experiment (PB-DOE) method for the sensitivity analysis of a device and a circuit performance to inter- and intra-die process variations. Further, it is shown that PB-DOE method takes relatively less computational time and provides reasonable accuracy as compared to standard Monte Carlo Method. In the next part of the work, computationally efficient methodology for timing yield analysis of standard CMOS cells is proposed. The proposed technique combines well-known statistical methods namely Principal Component Analysis (PCA) and PB-DOE method. Here, the proposed technique is successfully implemented for timing yield estimation of standard CMOS cell implemented in non-planar Double-Gate (DG) FinFET technology. However, our methodology is independent of technology platform and can be implemented on classical bulk CMOS technology or any other emerging technologies too. Furthermore, it is shown that the proposed methodology reduces the computational cost by 35% as compared RSM based Monte Carlo method.

Digitally controlled variation tolerant timing generation technique for SRAM sense amplifiers

Abstract: Embedded memories occupy increasingly greater portion of SoC area, significantly affecting system performance metrics such as speed and power. The adverse effects of variation, that is accompanying technology scaling, is however making design of these high density memories increasingly challenging. The speed and power consumption of memories is greatly affected by the technique employed to generate timing signals, specifically the sense-amplifier enable (SAE) signal. A BIST based post-silicon tunable approach is known to provide the best tracking with process variation with minimum margins. This paper proposes an improved tuning algorithm that utilizes random-sampling to achieve faster tuning. The algorithm also enables increased utilization of redundancy repair infrastructure to further lower power consumption and improve access speeds.

A wideband multi-stage inverter-based driver amplifier for IEEE 802.22 WRAN transmitters

Abstract: This paper proposes a wideband multi-stage inverter-based driver amplifier (DA) suitable for IEEE 802.22 wireless regional area network (WRAN) transmitters. In order to optimize the voltage gain, power, linearity and load drivability, the DA employs two cascaded inverters followed by a source follower, in which the second inverter employs resistive feedback and an inverter-based active load to achieve linearization. Simulated in 65 nm CMOS, the achieved voltage gain is 17.6 dB and the power is 14.6 mW at 1.2 V. The -3 dB bandwidth is 5.6 MHz to 2.17 GHz. For a 3rd-order intermodulation distortion (IMD3) of -45 dBc, the output power reaches -7.3 dBm.

Methods of optimized via design for higher channel bandwidth

Abstract: This paper analyzes the ability of an optimized via design to achieve higher channel bandwidth by minimizing the impedance discontinuity of a high speed serial link above 5Gbps owing to the parasitic capacitive effect of vias on a single Printed Circuit Board (PCB). The methods of optimized via design are back-drilling plated through hole, removing unused pads and increasing anti-pad clearance [1]. Different via features and their impact are studied in 3D model extraction using EMPro software from Agilent, and simulations are done using Advanced Design System (ADS) where the measurement of insertion loss, time domain reflectometry (TDR) and eye diagrams are used. Subsequently, the simulation results are correlated with measurement results from a prototype PCB.

External loopback testing on high speed serial interface

Abstract: Testing for high speed links have been, and will continue to be, primarily based on checking their conformance to the specifications and performance testing due to the lack of industry analog fault models. However, with the increased diversity of features to support new transceiver protocols, specification testing on high speed serial interface (HSSI) is becoming increasingly difficult and costly. Techniques like design-for-testability (DFT) have been applied to overcome some of these challenges. In this paper, the author presents case studies of one of the most common DFT techniques for HSSI testing, namely, external loopback. Firstly, the different flavors of loopback available in industry are briefly mentioned together with their usage. Next, the need for external loopback engagement in HSSI test strategy is described. This is then followed by the explanation of the external loopback circuitry on device-under-test (DUT) card and test methods for supporting HSSI buffer level testing that are implemented on transceiver based FPGA product. This paper also provides summary from silicon experiences and directions for future improvement.

High-quality data assignment to hierarchical memory organizations for multidimensional signal processing

Abstract: In real-time data-dominated communication and multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space - namely power consumption, performance, and chip area. Multi-layer memory hierarchies are used to reduce the energy consumption, but also to enhance the system performance. The energy-aware optimization of a hierarchical memory architecture implies the addition of layers of smaller and faster memories used to store the intensely-used data, in order to better exploit the non-uniform memory accesses. This paper presents an electronic design automation (EDA) methodology for energy-efficient signal assignment to the memory layers of a hierarchical storage organization. This approach starts from the behavioral specification of a given application and, employing algebraic techniques specific to the data-dependence analysis used in modern compilers, identifies those parts of (multidimensional) arrays intensely accessed. Tested on a two-layer memory hierarchy, this EDA methodology led to savings of storage energy consumption from 40 % to over 60 % relative to the energy used in the case of flat memory designs.

Cluster-based thermal-aware 3D-floorplanning technique with post-floorplan TTSV insertion at via-channels

Abstract: In 3D-IC architecture, thermal issues largely affect design reliability. The three-dimensional structure impedes heat dissipation and leads to high temperature when designs in execution. In this paper, we propose a cluster-based 3D-floorplanning approach to place modules based on the factors of area, wire-length, and power density. Then we construct a precise thermal conduction model to compute temperature distribution in terms of the resultant floorplan. The thermal-vias will be placed at some reserved regions, called via-channels, by analytical computation based on temperature distribution. The thermal-via insertion procedure will repeat until the peak temperature is acceptable. The experimental results show that our framework is able to effectively reduce the peak temperature in hot-spots based on a precise temperature computation model.

Optimization of thermal vias for thermal resistance in FR-4 PCBs

Abstract: A detailed thermal simulation of the performance of FR-4 PCBs having various "via configuration" is made in this study. The results indicate the thermal resistance from the simulation is significantly affected by compact thermal via configurations. Thermal resistance can be improved by increasing via number and also with copper filled via. For further explanation of the significant drop of thermal resistance at PCBs with thermal via, the detailed thermal resistance distribution at the thermal module are further examined. The significant drop in thermal resistance mainly occur in FR-4 PCBs with the help of thermal via. However, there is observed a maximum number of via which contribute to optimized thermal resistance across the PCB.

Multiobjective evolutionary approach to silicon solar cell design optimization

Abstract: In this study, we implement a device simulation-based multi-objective evolutionary algorithm (MOEA) for the optimal design of silicon solar cells. The short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated and used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm in the unified optimization framework. Designing parameters, the material and structural parameters are simultaneously optimized for the explored solar cells. Our device simulation-based MOEA methodology is useful, compared with the conventional genetic algorithm, in the solar cell design optimization.

Optimized clock gating cell for low power design in nanoscale CMOS technology

Abstract: This paper discusses a novel clock gating cell (CGC) optimized for high performance and low power design. The conventional CGC is analyzed along with other low power implementations of the CGC that have previously been proposed. The new CGC topology is proposed and compared to the topologies previously introduced in terms of dynamic clock power, leakage, area and timing.

A new TSV set architecture for high reliability

Abstract: Recently, 3D IC design is a very attracting issue, and the importance of system reliability increases. This paper proposes a new reliable and repairable TSV set architecture. The proposed architecture supports the previous TSV repair scheme using TSV redundancies and provides a defect/error detection function reutilizing residual TSV redundancies for high reliability of 3D ICs. This can be applied to both online test and soft error detection/analysis. The results show that the proposed TSV set architecture guarantees high TSV redundancy efficiency and reliability. And, the results show that the proposed TSV architecture achieves defect/error coverages which are steady and predictable by a simple formula.

Heat transfer in high-power LED with thermally conductive particle-filled epoxy composite as thermal interface material for system-level analysis

Abstract: This paper elucidates the thermal behaviour of an LED employing different particles filled epoxy as thermal interface material (TIM) for enhanced heat dissipation. Highly thermal conductive metal filler of aluminium (Al) and ceramic fillers of aluminium nitride (AlN) and aluminium oxide (Al2O3) were incorporated in bisphenol A diglycidylether (DGEBA) epoxy resin to identify the effect of the filler materials as TIM on the thermal performance of high power LEDs. From the thermal transient analysis of a 3W warm white LED, it was observed that the Al filled composite exhibits the lowest junction temperature of 38.3 °C compared to the other two fillers. The total thermal resistance of the package with AlN filled composite and Al2O3 filled composite were 13.77 and 15.50K/W respectively. This paper too suggests that the total thermal resistance of the LED package increases when the particle size of the fillers decrease.

A 128-phase delay-locked loop with cyclic VCDL

Abstract: A multiphase delay-locked loop with cyclic voltage controlled delay line is presented in this paper. The 128 output phases can be simultaneously produced by the 16-delay units of VCDL. The presented multi-phase DLL is realized by CMOS 90 nm 1P9M process. The total power consumption is 9.2 mW at the supply voltage of 1.2 V and the operational frequency of 92.16 MHz.

On improving at no cost the quality of products built with SRAM-based FPGAs

Abstract: Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based FPGAs that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the dependability with respect to configuration errors, at no cost, by selectively hardening parts of the design. The selection of locally duplicated functions is made so that the protections take advantage of FPGA resources that would not be used by the implemented design. An automated design flow is presented for Xilinx Virtex V devices and fault injection results show that the design dependability may be noticeably enhanced. As an example, more than 40% of the LUTs used to implement a Leon3 Sparc v8 processor can be protected against multiple configuration errors with less than 20% resource overheads at the block level. The final system-level overhead may in many cases be null for a given product, either due to the discrete sizes of available FPGAs or to a different repartition of resource budget between system blocks.

A fast transient response synchronous Buck converter with modified ripple-based control (MRBC) technique

Abstract: A new ripple controlled synchronous Buck converter featuring with improved transient response and low output voltage ripple is presented in this paper. The proposed modified ripple-based control (MRBC) technique adopting a novel ripple generate mechanism realizes the fast response ability by regulating the inductor current and output voltage through separate loops rapidly. In addition, a high-precision current sensor is utilized to form the current loop to improve the regulation accuracy. Meanwhile, the output voltage ripple is minimized by eliminating the requirement of a large ESR (equivalent series resistance) thanks to the introduced current loop. The proposed controller is implemented in a 0.5 μm BCD process of CSMC. Simulation results show that, during a 500 mA load current step change, the controller is able to regulate the output voltage to return to its nominal value within 2.6 μs with less than 50 mV overshoot/undershoot. The output voltage ripple is only 15 mV.

Variability aware performance evaluation of low power SRAM cell

Abstract: Till today CMOS scaling is considered as the best option to achieve higher density, high performance and low power integrated circuits. However, scaling of conventional planar MOSFET in the sub-45nm regime leads to many undesirable short channel effects. FinFET is considered as the suitable candidate for the replacement of conventional planar MOSFETs. In this work, suitability of FinFETs for replacement of planar bulk technology in sub-20nm regime has been verified using Predictive Technology Models. For this purpose, the performance of the FinFET based SRAM cell is compared with conventional planar Bulk based SRAM cell. Moreover, robustness of FinFET based SRAM cell against process, temperature and power supply variations is evaluated and compared with conventional planar based SRAM cell. Our simulation results confirms the suitability of FinFETs for the replacement of conventional planar CMOS technology.

Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling

Abstract: With increasing computing power in mobile devices, conserving battery power (or extending battery life) has become crucial. This together with the fact that most applications running on these mobile devices are increasingly error tolerant, has created immense interest in stochastic (or inexact) computing. In this paper, we present a framework wherein, the devices can operate at varying error tolerant modes while significantly reducing the power dissipated. Further, in very deep sub-micron technologies, temperature has a crucial role in both performance and power. The proposed framework presents a novel layered synthesis optimization coupled with temperature aware supply and body bias voltage scaling to operate the design at various “tunable” error tolerant modes. We implement the proposed technique on a H.264 decoder block in industrial 28nm low leakage technology node, and demonstrate reductions in total power varying from 30% to 45%, while changing the operating mode from exact computing to inaccurate/error-tolerant computing.

Port assignment for multiplexer and interconnection optimization

Abstract: Data path connection elements usually consume a significant amount of both power and area on a VLSI chip. In this paper, we focus on the port assignment problem for multiplexer (MUX) and interconnection optimization in High-Level Synthesis. Given a binding solution of operations and variables, the port assignment problem connects the registers to the operator ports through MUXes, to minimize the interconnections between MUXes and operator ports, as well as the MUX power and area. We formulate the port assignment problem for binary commutative operators as a vertex partition problem on a graph, and propose a local search based heuristic algorithm that iteratively performs the elementary spanning tree transformation on the graph to solve it. We also propose a method to estimate the result of the tree transformation and filter a considerable amount of bad solutions in advance which greatly accelerate the algorithm. The experimental results show that our proposed algorithm is able to achieve 48% execution time reduction and 8.3% power reduction compared with the previous work, and the power reduction can be obtained for 37% test benches.