Showing papers presented at "Asia Symposium on Quality Electronic Design in 2015"

An accurate detailed routing routability prediction model in placement

Abstract: Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult due to the complexity and uncertainty of routing. In this paper, we propose a new detailed routing routability prediction model based on supervised learning. After extracting key features in placement and detailed routing, multivariate adaptive regression is performed to train the connection between these two stages. Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage. Experiments show that our average prediction accuracy is 79.8%, which is comparable with other state-of-art routability estimation techniques.

Compact FPGA implementation of PRESENT with Boolean S-Box

Abstract: Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform Our proposed design uses an 8-bit datapath to reduce hardware size Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping Further factorization is also done to reduce the size of the Boolean S-Box As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform Our design also features a respectable throughput of 5132 Mbps at the maximum frequency of 236574 MHz

Combined SRAM read/write assist techniques for near/sub-threshold voltage operation

Abstract: This paper investigates the use of combined read and write assist techniques to reduce the minimum operating voltage (V MIN ) of the 6T SRAM bit-cell. While write failures initially limit V MIN , applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling V MIN down to near/sub threshold voltages. We find that combining negative bitline (BL) for write assist with array V DD boosting for read assist is most effective for reducing the array V MIN and eliminating half-select failures for commercial 130nm and sub-20nm FinFET technologies across different process corners and temperatures. The proposed combination results in the highest reduction in SRAM V MIN (to 300mV for FinFET and to 600mV for 130nm CMOS). This paper also shows that controlling the degree of applied assist based on the chip corner will allow further reductions in V MIN for the 130nm CMOS (to 450mV) and the required assist needed to achieve V MIN for both the FinFET and the 130nm bit-cells.

Design for reliablity: A novel counter matrix code for FPGA based quality applications

Abstract: The scaling down of semiconductor technology in FPGA increases the soft errors due to radiation effects in space To address this technological challenge a novel coding technique, Counter Matrix Code (CMC) is proposed to protect the SRAM based FPGA's configuration memories (FCM) against radiation induced Multiple Bit Upsets (MBU) with Low cost and maximum correction capability The proposed CMC is experimentally studied for its efficiency and reliability The proposed technique improves the reliability of the memory by more than 7× compared to traditional HC technique and more than 4× compared to MC and more than 2× compared to DMC The cost of the proposed work is less than traditional DMC and MC

Current-mode simultaneous bidirectional transceiver for on-chip global interconnects

Abstract: A new current-mode simultaneous bidirectional transceiver for high speed asynchronous communication over on-chip global interconnects has been proposed in this paper. The new transceiver can receive and transmit the data simultaneously over a same differential interconnect, thereby decreasing the number of interconnects required compared to unidirectional signalling schemes. The transceiver provides a low input impedance and so supports high bandwidth of transmission. The circuit has been implemented in 65nm UMC process with a global interconnect of length 5mm and width 1.5μm. The energy efficiency of the transceiver for simultaneous bidirectional data transmission of 10 Gbps data is 0.38 pJ/b.

Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS

Abstract: This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“V dd ”) down to 84 mV The low V dd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (“RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low V dd potential According to simulations, the energy per operation could be down to about 15 fJ/bit for the implementation, based on L = 80 nm For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 185 to 47 % higher than the RCA having L = 80 nm The area was 97 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA

A field-based parasitic capacitance model with 3-D terminal and terminal fringe components

Abstract: In this paper, a parasitic capacitance model for a single three-dimensional (3-D) wire above a plate is developed The model decomposes electric field into various regions and gives solutions to each part The total capacitance is the summation of all capacitance parts corresponding to the electric field distribution The model's physical base minimizes its complexity and error comparing to a traditional empirical fitting process Verified by extensive COMSOL simulations, the model can accurately predict parasitic capacitance for a wide range of BEOL wire dimensions Thus, it holds potential to be further investigated for circuit simulation and design

On enhancing the reliability of digital microfluidic biochips (DMFB) through electrode cells health classification

Abstract: Reliability of digital microfluidic biochips (DMFB) emerges to be a critical issue, as they are becoming a popular alternative for laboratory experiments like DNA analysis, immunoassays and safety critical clinical diagnostics. To improve DMFB reliability, the key is to know the possible points of failure of its electrode cells. In this paper, a novel test methodology is introduced to monitor the health of the DMFB by classifying its individual cells into weak, faulty and fault-free. The emphasis is on identifying physically degraded cells in the DMFB array and reducing their over-use, thus saving those cells from becoming faulty during operation. Degradation in cell health is measured by the change in its capacitance via a capacitance measurement circuit that can be integrated with the DMFB. The paper also presents the circuit to classify the cells as weak, faulty and fault free, implemented using 180nm technology.

Detection of intermittent resistive faults in electronic systems based on the mixed-signal boundary-scan standard

Abstract: In avionics, like glide computers, the problem of No Faults Found (NFF) is a very serious and extremely costly affair. The rare occurrences and short bursts of these faults are the most difficult ones to detect and diagnose in the testing arena. Several techniques are now being developed in ICs by us to cope with one particular category of NFFs, being the intermittent resistive faults (IRF). The reuse of these (on-chip) embedded instruments for detection of these faults at the board-level has been investigated in conjunction with the possibilities of enhancing the (mixed-signal) boundary-scan standard IEEE 1149.4. This paper will explore how this can be accomplished.

Testing power-delivery TSVs

Abstract: Many TSVs in a 3D IC are not used for signal transmission but for power delivery. Techniques needed to detect them have not been studied in-depth in the literature. In this paper, we present a test method for power-delivery TSVs, by embedding ring-oscillator (RO) based monitors (in a scalable architecture) to detect if there is any excessive voltage-drop at the end of any TSV during a manufacturing test session. One key feature as opposed to previous RO-based methods is that our approach is able to detect the worst-case dynamic voltage-drop (occurring in a very short period of time such as 1ns), rather than just the average voltage-drop over a long period of time. This is essential in order to detect small defects inside the power delivery network. These defects, if not detected, could set off a transient timing failure when the IC is operated in a system.

A wide input voltage range start-up circuit for solar energy harvesting system

Abstract: This paper presents design of an improved start-up circuit for a micro scale solar energy harvesting system. A wide input voltage range (270mV–1.8V) start-up circuit that can work in strong as well as weak illumination levels without causing any stress and reliability issues to the CMOS devices has been proposed. The use of native device (zero-V th ) and ultra-low power Band-gap Reference (BGR) helps to operate the start-up circuit within 1.8V maximum voltage allowed by 40nm CMOS technology. The complete system works with minimum power of 2.841μW at 270mV in start-up mode and works with minimum voltage of 100mV once the system enters into main converter mode. The system uses fractional open circuit voltage method (FOCV) to extract maximum power from solar cell when operating in main converter mode.

True 3D antenna for UHF RFID application

Abstract: This paper presented a new kind of Omni-directional UHF RFID tag antenna. The antenna is composed of four identical arrow-shape modules that are completely center-symmetric. Compared with the traditional dipole planar antenna, the antenna proposed has a −10dB bandwidth at 244MHz and shows better performance in Omni-direction in the reading range. The new Omni-directional UHF RFID tag antenna can effectively eliminate the reading blind spots caused by the antenna direction.

An efficient buffer sizing algorithm for clock trees considering process variations

Abstract: As VLSI technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. Clock skew resulted by process variations can be significantly different from the nominal value. In this paper, we propose an efficient buffer sizing algorithm to solve the skew optimization problem in presence of process variations. By analyzing the influence of process variations on wire delay and buffer delay, we make a quantitative estimation of the skew distribution under Monte-Carlo SPICE simulations. The number and size of buffers on some critical paths are rearranged to reduce the skew results under process variations. Experiment results which are evaluated on ISPD 2010 benchmarks show that our algorithm achieves a significant 58% reduction on worst skew with only 6% increase on power consumption.

A pipelined CORDIC architecture and its implementation in all-digital FM modulator-demodulator

Abstract: COordinate Rotation DIgital Computer (CORDIC), is an algorithm that is used to perform trigonometric-related calculations. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of CORDIC algorithm using pipelined architecture. The pipelined CORDIC is then used in an all-digital FM modulator-demodulator. All designs are implemented in Verilog and synthesized by using Altera Quartus software with DE2-70 FPGA target board. The proposed design consumes 1,103 logic element, latency 33.32 ns, and maximum frequency 420.17 MHz. The overall system including FM modulator-demodulator utilizes 3,911 logic elements, latency 233.33 ns, and maximum frequency 60 MHz.

Architectural error prediction using probabilistic error masking matrices

Abstract: Reliability has emerged as an important design criterion due to shrinking device dimensions To address this challenge, researchers have proposed techniques compromising the Quality-of-Service across all design abstractions Performing cross-layer reliability-QoS trade-off is a major challenge, which requires strong understanding of the fault propagation through different design abstractions In this paper, we propose an analytical error prediction framework, based on probabilistic error masking matrices The prediction is performed by propagating erroneous tokens through abstract logic networks We report detailed experiments using a RISC processor and several embedded applications The proposed approach demonstrates significantly faster reliability evaluation compared to pure simulation-driven approach, while predicts the erroneous effects of injected faults in both architecture and application levels Several novel techniques are also proposed to increase the accuracy of error prediction

SER mitigation technique through selective flip-flop replacement

Abstract: The advancement in the semiconductor manufacturing process has reduced the device dimensions, which in turn has reduced design and manufacturing costs of the Integrated Chips (IC). This has accelerated the IC penetration in automobiles, health care and safety critical systems. However, the smaller device dimensions have made the ICs vulnerable to soft-errors. The sequential cells in a given design contribute significantly to its soft-error rate (SER). Some of the soft-errors get masked and do not cause any adverse impact. The masking can occur due to logic or timing reasons. This paper presents a flow that uses the Timing Vulnerability Factor (TVF) and Architecture Vulnerability Factor (AVF) of the sequential instances in a given design to reduce its soft-error rate (SER). The paper proposes a novel method to efficiently compute the TVF and AVF parameters followed by a linear programming technique that uses these parameters to reduce the SER of the given design. Using the proposed technique, we have reduced the sequential cell contribution to the SER of an in-house IP design by 36% for an increase of 9% in sequential cells area.

A new 600V partial SOI LDMOS with step-doped drift region

Abstract: A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped profile induces an electric field peak in the surface of the device, which can improve the surface field distribution and the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance. The proposed LDMOS transistor with SDD in partial PSOI (SDD-PSOI) is analyzed by 2-D numerical simulations, compared with conventional SOI (CSOI) and conventional PSOI (CPSOI) LDMOS transistors. The results indicate that the proposed structure can significantly improve BV up to 607V and reduce on-resistance by 12.6% in comparison to CPSOI.

Performance analysis of 22 nm deep submicron NMOS transistors

Abstract: We present the design and analysis of 22 nm deep submicron indium gallium nitride InGaN and silicon Si NMOS transistors. The results show that the saturation and breakdown behavior of the InGaN transistor is significantly higher than that of its silicon Si counterpart. Our analysis suggests that InGaN could be a better alternative substrate material in the design and fabrication of transistors, as the size of the channel approaches the mean free path of the carriers.

High voltage MOS modeling with BSIM4 sub-circuit model

Abstract: This paper presents a technique for modeling highvoltage MOS (HVMOS) devices with BSIM4 sub-circuit model Two voltage-dependent resistors, rd and rs are added into the drain and source side of a core BSIM4 model to capture the high voltage effects; quasi-saturation (QS) and self-heating effect (SHE) We use rd to capture QS The voltage drop across rd captures the actual physical effect that causes QS To model SHE, we use a new empirical method Rs is used to ensure the effective drain-to-source voltage (Vds_eff) and effective gate-to-source voltage (Vgs_eff) drop about the same amount at saturation point Hence, the saturation point remained unchanged When Vds further increases after the saturation point, the Vd drop across rs is larger and reduces Id further This causes an effect similar to SHE By applying the proposed methodology, we are able to fit the silicon data We also discuss the methodology to model the SHE dynamic effect by introducing a capacitor (cs) in parallel with rs When Vd pulse is applied at the Vd, cs is being charged and almost no current flowing through rs Hence, no SHE at that time When cs is fully charged, then rs takes effect This captures the dynamic characteristics of SHE

Clock gating assertion check: An approach towards achieving faster verification closure on clock gating functionality

Abstract: Clock gating is a power reduction technique widely used in Register Transfer Level (RTL) stage of a chip design. The addition of clock gating logics has increased the complexity of a design and therefore requires considerable amount of verification effort. Furthermore, the scoreboard checking mechanism in Open Verification Methodology (OVM) verification environment still lacks the capability to completely comprehend the checking of clock gating logics correctness. To address this, a verification method, called Clock Gating Assertion Check (CGAC) method, independent of verification environment is proposed aiming at achieving a faster pre-silicon verification closure on clock gating logics with minimum verification effort. The proposed method is an automated flow using codes written in Hardware Description Language (HDL) in RTL stage and clock domains information of a design as the main inputs to generate checks at possible clock gating boundary conditions. The CGAC method was used to verify the clock gating logics of an existing Soft Intellectual Property (SIP) design. The implementation details of the method are discussed in this paper. By using the method, a total of 4 clock gating bugs were found and analysis on the impacts of the bugs is discussed. As a conclusion, the proposed method is proven effective in ensuring the correct clock gating implementation in a design.

PrimeTime web-based report analyzer (PTWRA) tool

Abstract: In modern VLSI designs, timing closure has become a challenging and tedious task for the designers due to the fact that the number of design logic gates led to an exponential increase in the number of timing paths. PrimeTime from Synopsys is used to perform Static Timing Analysis and to generate a timing report in the form of large size text file; hence, data analysis is a complex task for the designer. This work presents a web-based text-mining software tool based on text-mining and web-based reporting techniques. It consists of two parts, the Perl software parser file in the user part, while MySQL and Apache servers in the server part. This tool parses Synopsys PrimeTime timing report and provides analysis services for team collaboration, clock skew and path constraints calculations, paths categorization and paths distribution in well-organized tables, and presents data on website pages.

Non-linearity analysis of stochastic time-to-digital converter

Abstract: Stochastic TDCs excel in high resolution at narrow dynamic ranges by employing comparators which have their decision influenced by PVT variations. As the functionality relies on these variations, a transfer function akin to the Gaussian distribution ensues, which is non-linear. We propose a theoretical derivation of the non-linearity analysis and use it to find the stochastic TDC's effective resolution and optimal dynamic range. Software and circuit Monte Carlo simulations are conducted in support of the theoretical findings, where the circuit employs comparators implemented in 180nm CMOS technology.

Automatic register balancing in model-based high-level synthesis

Abstract: The designer sometimes wants to insert register(s) in specific location(s) of a design in order to break critical paths To do so, the designer has to manually insert registers in all parallel paths as well to balance registers in all paths to keep the functionality of the design intact This task is known as ‘register balancing’ in the design community The design size, complexity and hierarchy make manual register balancing in parallel paths task complex and error prone The method presented here automatically inserts register(s) in the user specified location(s) and also automatically balances registers in all parallel paths The register balancing problem has been suitably mapped to global retiming problem and solved using standard global retiming algorithm The proposed method has been implemented in a model based high-level synthesis tool and tested on several Simulink designs

Fully-hybrid computer-aided RF LNA design and evaluation for GSM-1900 standard band

Abstract: A fully hybrid computer-aided circuit design to achieve a first-pass on-board CMOS LNA fabrication is studied The LNA is implemented in 013-μm CMOS process A post-layout die-level electromagnetic-field analysis, to extract the interconnection and interaction parasitic between on-chip components, is used The extracted touchstone model is integrated with circuit model of board including the microstrip lines and surface-mounted passive elements as well as the electromagnetic-field extracted model of radio-frequency coaxial connectors The hybrid electromagnetic-circuit simulation results are compared with the measurement results for evaluation The comparison presented an excellent correlation between the simulated and measured results The connector's effects can be de-embedded using its developed electromagnetic model This method of simulation and optimization is targeted to achieve first-pass run instead of optimization using costly prototypes

An on-chip transfer function measurement of PLLs with triangular modulated stimulus

Abstract: This paper proposes an on-chip measurement method of PLL transfer function. In our proposed scheme, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the amplitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against PVT variations. MATLAB simulation results demonstrated the measurement of the transfer function.

Method to improve ball grid array Imax distribution for small form factor package design

Abstract: Maximum current (Imax) distribution across substrate has been one of the major design factors that govern the electronic package form factor. Particularly on ball grid array (BGA) package design, often times Imax distribution determines the number of solder balls required for each interface to sustain respective workloads hence defines the total ball count and the x-y dimension of the electronic package. This paper introduces a new method to improve BGA Imax distribution while keeping ball count minimal for to enable small form-factor package design. The proposed solution utilizes fundamental of electrical resistance control through on-board BGA pad design customization to achieve more uniform Imax distribution across solder balls and enable up-to 25% Imax reduction with negligible IR drop impact. Power losses across plane were also simulated and compared against conventional design in this study.

Resonant power supply noise cancelling with noise detector based in DLL and vernier TDC

Abstract: This paper proposes an active resonant power supply noise cancelling with fast voltage drop sensor using the combination of delay-locked loop (DLL) and vernier time-to-digital converter (TDC). Also, we propose the capacitor selector circuit realizing the active insertion of capacitors in less silicon area. These components enable one clock noise detection with fine resolution. Simulation results show that our noise sensor detects 54 mV voltage drop in one clock cycle and cancels 28% of the supply noise by the active charge injection. The proposed circuits use the silicon area about 27 times more effectively than conventional passive decaps.

An all-digital adaptive approach to combat aging effects in clock networks

Abstract: In this paper, we analyze the impact of asymmetrical aging due to Bias Temperature Instability (BTI) in the clock tree segments of power efficient designs. The nonuniform aging of launch and capture clock segments could not only violate the setup timing but also result in gross hold violations. Aging in clock networks also results in pulse width compression which impacts the half-cycle paths' timing adversely. We present a reference-less alldigital technique to detect the aging effects and measure quantitatively the extent of pulse-width-distortion. The measurement results are then applied to rectify the pulse width distortion such that the clock network output is restored to a 50-50 duty cycle. The technique is validated using SPICE simulation based on 45nm industry standard library. A resolution of sub-1ps is achievable for both distortion measurement and correction circuits.

Realization of non-linear i-v curve with low power dissipation using linear ion drift memristor model

Abstract: Modern memories are very power hungry, larger in size, low retention period, low chip density and high cost Memristor is a missing passive circuit element and regarded as a new class of emerging non-volatile memories overcoming the above problems Memristor may be thought of an active as well as passive device based on the conditions of Memristance and Dynamic Negative Differential Resistance (DNDR) Memristor has been used for non-volatile memory applications, if and only if it produces non-linear pinched hysteresis curve If the size of the pinched hysteresis curve increases, power dissipation increases as well In this paper, we discuss the parametric analysis of memristor adopting the linear ion-drift model to achieve low power dissipation while retaining the nonlinear i-v characteristics

Radio-frequency silicon-based CMOS-compatible MEMS variable solenoid micro-fluidic inductor with Galinstan-based continuously-adjustable turn-ratio technique

Abstract: This paper proposes a continuously-variable MEMS solenoid inductor with resonating frequency of over 8 GHz. This inductor allows high-tuning capability for resonance adjustment purpose in reconfigurable radio-frequency circuit devices. To achieve this goal, a channel is contrived to bypass the turns of the coil through the injection of a conductive liquid (here, Galinstan). Once the number of turns decreases, the inductance value falls according to the injection level. The proposed solenoid inductor is simulated using a full-wave three-dimensional electromagnetic analysis tool, HFSS, for silicon substrate with copper metallic coil for different level of conductive liquid injection. Beside the cost-effective and easy manufacturing process, the simulation results demonstrate the 150% tuning range. The EM simulation results show a maximum quality factor of 85 at 3 GHz for proposed inductor. The minimum and maximum inductance values are 1.5 and 4 nH at 4 GHz for low-resistivity Silicon. This tunable inductor can be applied into reconfigurable radio-frequency circuits and matching networks to tune the operating frequency of the system.