Asian Solid-State Circuits Conference 

About: Asian Solid-State Circuits Conference is an academic conference. The conference publishes majorly in the area(s): CMOS & Phase-locked loop. Over the lifetime, 1577 publications have been published by the conference receiving 16405 citations.

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

Abstract: A high-efficiency CMOS rectifier circuit for UHF RFIDs was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input. A differential-drive active gate bias mechanism simultaneously enables both low ON-resistance and small reverse leakage of diode-connected MOS transistors, resulting in large power conversion efficiency (PCE), especially under small RF input power conditions. A test circuit of the proposed differential-drive rectifier was fabricated with 0.18 mu m CMOS technology, and the measured performance was compared with those of other types of rectifiers. Dependence of the PCE on the input RF signal frequency, output loading conditions and transistor sizing was also evaluated. At the single-stage configuration, 67.5% of PCE was achieved under conditions of 953 MHz, - 12.5 dBm RF input and 10 KOmega output load. This is twice as large as that of the state-of-the-art rectifier circuit. The peak PCE increases with a decrease in operation frequency and with an increase in output load resistance. In addition, experimental results show the existence of an optimum transistor size in accordance with the output loading conditions. The multi-stage configuration for larger output DC voltage is also presented.

A low-noise self-calibrating dynamic comparator for high-speed ADCs

Abstract: This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.

A 8-bit 500-KS/s low power SAR ADC for bio-medical applications

Abstract: This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications An energy-saving switching sequence technique is proposed to achieve low power consumption The average switching energy of the capacitor array can be reduced by 56% compared to a conventional switching method The measured signal-to-noise-and-distortion ratios of the ADC is 4692 dB at 500 KS/s sampling rate with an ultra-low power consumption of only 775-muW from a 1-V supply voltage The ADC is fabricated in a 018-mum CMOS technology

High efficiency CMOS rectifier circuit with self-Vth-cancellation and power regulation functions for UHF RFIDs

Abstract: High efficiency CMOS rectifier circuit for UHF RFID applications has been developed The rectifier utilizes self Vth cancellation (SVC) scheme in which threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated by output voltage of the rectifier itself Very simple circuit configuration and no power dissipation feature of the scheme enable excellent power conversion efficiency (PCE) especially in small RF input power conditions At higher RF input power conditions, PCE of the rectifier automatically decreases This is the built-in self-power-regulation function Proposed SVC CMOS rectifier has been fabricated with 035 mum CMOS process and the measured performance has been compared with other types of rectifiers The SVC CMOS rectifier achieves 29% PCE at -99 dBm RF input power condition This PCE is larger than ever reported rectifiers under the condition

A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule

Abstract: This paper proposes an architecture of the wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring. The low-power digital IC design inside the wireless endoscopic capsule is discussed in detail. A very large scale integration (VLSI) architecture of three-stage clock management is applied, which can save 46% power inside the capsule compared with the design without such a low-power design. A stoppable ring crystal oscillator with minimal overhead is used in the sleep mode, which results in about 60-muW system power dissipation in sleep mode. A new image compression algorithm based on Bayer image format and its corresponding VLSI architecture are both proposed for low-power, high-data volume. Thus, 8 frames per second with 320*288 pixels can be transmitted with 2 Mb/s. The digital IC design also assures that the capsule has many flexible and useful functions for clinical application. The digital circuits were verified on field-programmable gate arrays and have been implemented in 0.18-mum CMOS process with 6.2 mW