Defect and Fault Tolerance in VLSI and Nanotechnology Systems 

About: Defect and Fault Tolerance in VLSI and Nanotechnology Systems is an academic conference. The conference publishes majorly in the area(s): Fault tolerance & Fault coverage. Over the lifetime, 1317 publications have been published by the conference receiving 15574 citations.

Soft-error detection using control flow assertions

Abstract: Over the last few years, an increasing number of safety-critical tasks have been demanded of computer systems. In this paper, a software-based approach for developing safety-critical applications is analyzed. The technique is based on the introduction of additional executable assertions to check the correct execution of the program control flow. By applying the proposed technique, several benchmark applications have been hardened against transient errors. Fault injection campaigns have been performed to evaluate the fault detection capability of the proposed technique in comparison with state-of-the-art alternative assertion-based methods. Experimental results show that the proposed approach is far more effective than the other considered techniques in terms of fault detection capability, at the cost of a limited increase in memory requirements and in performance overhead.

Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis

Abstract: This paper addresses a new threat to the security of integrated circuits (ICs). The migration of IC fabrication to untrusted foundries has made ICs vulnerable to malicious alterations, that could, under specific conditions, result infunctional changes and/or catastrophic failure of the system in which they are embedded. Such malicious alternations and inclusions are referred to as Hardware Trojans. In this paper, we propose a current integration methodology to observe Trojan activity in the circuit and a localized current analysis approach to isolate the Trojan. Our simulation results considering process variations show that with a very small number of clock cycles the method can detect hardware Trojans as small as few gates without fully activating them. However, for very small Trojan circuits with less than few gates, process variations could negatively impact the detection and isolation process.

Soft-error detection through software fault-tolerance techniques

Abstract: The paper describes a systematic approach for automatically introducing data and code redundancy into an existing program written using a high-level language. The transformations aim at making the program able to detect most of the soft-errors affecting data and code, independently of the Error Detection Mechanisms (EDMs) possibly implemented by the hardware. Since the transformations can be automatically applied as a pre-compilation phase, the programmer is freed from the cost and responsibility of introducing suitable EDMs in its code. Preliminary experimental results are reported, showing the fault coverage obtained by the method, as well as some figures concerning the slow-down and code size increase it causes.

Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS

Abstract: With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65 nm and 45 nm technology nodes at different supply voltages using the Qcrit based simulation methodology. The Qcrit for both bit cells and latches decreases by ~30% as the designs are scaled from 65 nm to 45 nm. This decrease is expected to continue with further technology scaling as well. The results show that at nominal voltage, the Qcrit for a latch is just ~20% more than that of the bit cell in sub-65nm technology nodes. Further, as the voltage is scaled from 1 V to 0.4 V, Qcrit decreases by ~5X which substantially increases the probability of an upset if a particle strike happens. This work shows that in sub-65 nm technology nodes with aggressive voltage scaling, it is equally critical to solve the soft error problems in logic (latches, flip-flops) as it is in SRAMs.

TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs

Abstract: This paper presents the adoption of the triple modular redundancy coupled with the partial dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique to the device under consideration. The application to a case study is presented and used to exemplify the proposed approach.