Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2008"

Co-Optimization of signal, power, and thermal distribution networks for 3D ICs

Abstract: Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solution to dramatically reduce the operating temperature of 3D ICs. In addition, designers use a highly complex hierarchical power distribution network in conjunction with decoupling capacitors to deliver currents. However, these thermal and power/ground interconnects together with those used for signal delivery compete with each other for routing resources including various types of Through-Silicon-Vias (TSVs). This paper presents the first work on routing with these multi-functional interconnects in 3D: signal, thermal, and power distribution networks. We demonstrate how to consider various physical, electrical, and thermo-mechanical requirements of these multi-functional interconnects to successfully complete routing while addressing various reliability concerns.

Stability analysis of the latency insertion method using a block matrix formulation

Abstract: The latency insertion method (LIM) has been demonstrated as an optimum algorithm for the transient simulation large networks. However, its stability is not unconditional. The method is analogous to the finite difference time domain (FDTD) used in electromagnetic. Stability depends on the proper choice of the time step. This paper examines the stability issues and presents an approach that allows a proper choice for the time step that will guarantee stability.

Sharing power distribution networks for enhanced power integrity by using Through-Silicon-Via

Abstract: This paper presents the excellent enhancement of power integrity (PI) by using through-silicon-via (TSV), which gives very small inductance to power distribution network (PDN) and consequently makes PDN impedance very low by sharing PDNs of 3-dimensionally (3-D) stacked chips. In this paper, the enhanced PI is shown by comparing that of wire-bonding applied 3-D stacked chips. A single SG (Signal/Ground)-TSV-pair shows very small serial inductance ( 4 pF) due to its thin SiO2 (0.2 ?m) between TSV and silicon substrate. In TSV applied 3-D multi-stacked chips case for high frequency application, the stability of PI becomes better than any other interconnection methods.

Signal integrity analysis of DDR3 high-speed memory module

Abstract: In this paper, a complete simulation methodology is introduced to analyze the signal integrity in a double data rate (DDR3) high-speed memory module. The equivalent models of the first-level package and various discontinuities in printed circuit board (PCB) are extracted, and then linked together by using general transmission-line models for the interconnections. Good agreements between the simulated and measured scattering parameters have confirmed the practicability of the simulation methodology. The fly-by structure is found to be crucial and thinner transmission lines around the synchronous dynamic random memory (SDRAM) region should be employed for achieving impedance matching with suitable design graph constructed accordingly. Finally, the effects of these models on the eye diagram are simulated to access their significance, for which the fly-by design is found to be the most critical, followed in order by package connections, via transitions, serpentine delay lines, and bends.

Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory

Abstract: The modeling methodology of power distribution system (PDS) in three different levels, chip, package, and PCB for Input/Output (I/O) interface of DDR3 high-speed memory is established. The simulation results are verified with measurement results in frequency domain. Good agreement between them is clearly seen. The co-simulation with three kinds of PDS at the I/O interface and off-chip driver (OCD) circuits is constructed for time-domain simulation. The input impedance of three different PDSs is shown, and the simulation results for voltage variation and eye-patterns are compared with the corresponding input impedance. It is found lower input impedance have better power and signal integrity for the high-speed memory interface circuits. The PDS co-simulation of chip-package-PCB is important for the DDR3 circuit design.

A study on broadband switching noise reduction by embedding high-density thin-film capacitor in a laminate package

Abstract: Broadband noise reduction has been investigated by embedding a high-density thin-film decoupling capacitor as much as 1 ?F in a laminate package. A complex programmable logic device (CPLD) was mounted on the laminate package instead of bare chip as a noise generating circuits. Then, the package was mounted on an evaluation board. Eight output buffer circuits of the CPLD were simultaneous switched. Switching noise between the power and ground pads on the package has been dramatically reduced by the existence of high-density thin-film decoupling capacitance inside the package.

A circuit model for ESD performance analysis of printed circuit boards

Abstract: This paper provides a SPICE-compatible circuit model for characterizing electrostatic discharge (ESD) clamping performance of protection devices mounted on printed circuit boards (PCBs). An equivalent circuit model for a commercial ESD generator is introduced and a simulation methodology of an ESD protection device with non-linear resistance characteristic using voltage controlled current source is described. These models combined to create a full circuit model with a PCB model in a SPICE-like circuit simulator. Comparison results between the simulated and measured are presented to verify the accuracy of the proposed circuit model. A trade-off analysis between the ESD clamping performance and signal integrity with the ESD protection device in high-speed applications is also presented as a case study.

Chip-package-board co-design - a DDR3 system design example from circuit designers’ perspective

Abstract: If package and board level parasitic models are not correctly included, as in many conventional design flows, the simulation results could be too optimistic as the impact from power and signal integrity (PI/SI) is underestimated. In addition, the process and temperature variations could further decrease design margins. In this paper, a detailed chip-package-board (CPB) parasitic model is applied at different process and temperature corners to investigate how PI/SI impacts input/output (I/O) performance of a 1.6-Gbps DDR3 memory system with the supply voltage at 1.5 V, where eye-opening (heye) is the major performance index number. The simulation results indicate that heye may differ as high as 58% if CPB parasitics are not properly modelled, where the issues would be more significant as I/O data rate increases to multi-gigabit-per-second.

Electro-thermal characterization of single-walled carbon nanotube (SWCNT) interconnect arrays

Abstract: We investigate electro-thermal properties of metallic single-walled carbon nanotube (SWCNT) interconnect arrays biased by a signal voltage in this paper, where temperature distribution, breakdown voltage, and current carrying capability are captured by solving one-dimensional heat conduction equation of the SWCNT. Two electro-thermal equivalent circuit models of single SWCNT and a SWCNT array are proposed to illustrate hybrid effects of SWCNT length, biasing voltage, and temperature on their signal integrities. Simulation results indicate that self-heating effect should be considered carefully in the design of local SWCNT array interconnect as it is biased by a high signal voltage.

A concise multiple scattering method for via array analysis in a circular plate pair

Abstract: Parallel plate modes are excited by the magnetic frill currents in the via holes (anti-pads). These modes are expressed as cylindrical waves. Multiple scattering of these modes among vias as well as from the edge boundaries of the plate pair are rigorously considered with the addition theorem of the cylindrical waves. An admittance matrix is derived for the via ports at the top/bottom surfaces of the via holes. Good agreement has been found between numerical simulations and the algorithm presented.

A low-cost approach for testing embedded rf passive circuits based on oscillation principle

Abstract: In this paper, a low-cost method for testing RF passive filters embedded in an RF substrate is proposed. As compared to a conventional test method the proposed method reduces the test-setup cost by around 35%. This method does not require any vector network analyzer (VNA) and allows the testing of embedded RF filters without any external test stimulus. A calibration technique is presented for an efficient implementation of the proposed method at the production floor. The core principle of the method is to include embedded passive filters through substrate surface probes into an external RF amplifier located on the probe card, such that this inclusion causes the RF amplifier to oscillate. RF filters are tested by measuring the changes in the oscillation frequency of the proposed test-setup. Hence, the test-setup cost reduces substantially. The test method with the calibration technique is demonstrated by simulations and measurements.

Novel and low cost through silicon via solution for wafer scale packaging of image sensors

Abstract: Solid state CMOS image sensor are being incorporated in an every increasing diversity of products. This paper presents a new TSV solution suitable for both single die and stacked die wafer-scale packages. So- called 'via-through-pad' interconnects are a novel form of interconnect that superficially resemble a TSV but the differences are important and have profound implications for the product cost and reliability. Unusually, the materials of the package construction are sourced from outside the semiconductor industry. This is done to keep costs as low as possible. The process technology is wholly scaleable so the same tool set can be used irrespective of the wafer diameter. Data will be presented showing via-through-pad interconnects are able to surpass by a wide margin, the exacting reliability requirements of the automotive industry, both at the package and board level.

Modeling of microcontroller with multiple power supply pins for conducted EMI simulations

Abstract: An EMC macro-model of a 16-bit microcontroller with multiple-power-supply pins has been proposed for estimating the conducted EMI from a power-supply network. The macro-model, called the linear equivalent circuit and current sources (LECCS) model, is composed of multiple circuit blocks and multiple current sources corresponding to the composition of the chip circuits in the microcontroller, i.e., a current source for a circuit block. A current source statistically expresses the total RF current occurring in the corresponding circuit block. We confirmed that the proposed model could correctly estimate the RF power-supply currents under different decoupling conditions up to 300 MHz. We also found that a linear circuit of the regulator between the I/O and core circuit blocks could express the RF coupling between the two blocks.

Investigation of an embedded RF switch IC in printed-circuit-board

Abstract: This paper presents the interconnection performance of the embedded integrated-circuit (IC) in printed-circuit-board (PCB) against wire-bonding method. Embedding IC into PCB substrate, micro-vias were adopted to interconnect the IC to the substrate. In order to consider the RF performance of the interconnection used for embedding IC into the PCB substrate, a double-pole-double-through (DPDT) switch IC was selected as an embedded RF IC. The insertion loss (IL) and the return loss (RL) of each switch were measured in order to compare the wire-bonded switch IC to the embedded switch IC. As a result, the wire-bonded switch IL is better than 0.7 dB and the RL is 16.2 dB at 5 GHz. The embedded switch IL is 0.6 dB and the RL is greater than 33.5 dB at 5 GHz. In addition to this, the embedded switch RL is better than 25 dB until 7 GHz. Thus the micro-via interconnection of the embedded switch in PCB substrate demonstrated better the RF performance than wire-bonding method in perspectives of the RL and the IL. This paper presents the advantages of the embedded IC in PCB by using micro-via.

LTCC-based triplexers for WiMAX front-end modules

Abstract: In this paper, we present low temperature co-fired ceramic (LTCC)-based triplexers for both transmit (TX) and receive (RX) paths in worldwide interoperability for microwave access (WiMAX) tri-band front-end modules. The triplexer for TX path consists of 2- and 5-GHz lowpass filters, a 3-GHz bandpass filter, and a matching network. All components are fully embedded in an LTCC substrate, and it occupies about 5.0 mm × 3.0 mm with a substrate thickness of 0.5 mm. The triplexer for TX path provides relatively low insertion loss at three passbands with a second-harmonic rejection of more than 30 dB. The triplexer for RX path is composed of three embedded bandpass filters and a matching network. The triplexer for RX path also provides low insertion loss at three passbands and high attenuation at other passbands. The size of the triplexer for RX path is about 5.0 mm × 4.0 mm × 0.5 mm. The measured results of the triplexers are in good agreement with the simulated results.

Enhanced wire bond transition from die to chip carrier for 3.1-10.6 GHz UWB applications

Abstract: We present in this paper a way to optimize the bandwidth of standard wire bond (WB) transition from die to chip carrier. This optimization is based on a simple lumped model of the WB transition taking into account the common ground impedance between the die and the chip carrier levels. The model also includes the magnetic coupling between the signal WB and the grounds WB. This model is validated by full wave electromagnetic simulations. On the basis of this lumped model simple guiding rules to increase the transition bandwidth are given. The signal integrity of the WB transition is enhanced and a return loss greater than 15 dB is obtained in the 3.1-10.6 GHz frequency band with standard WB lengths.

Power delivery for the next generation mobile platform

Abstract: Power delivery has become a key element for the mobile platform to improve battery life and meet the energy star requirements. In this abstract, we will show innovative modeling and design techniques to improve the energy efficiency of the mobile platform power delivery subsystem. These techniques includes better modeling of the on die voltage distribution and optimizing the power delivery subsystem by optimizing for the light load. We will also show measurements of typical systems demonstrating the need for drastic improvements in the notebook power delivery in the next few years.

An efficient and broadband slot antenna for 60 GHz wireless applications

Abstract: In this work, a single-layered CPW-fed slot antenna element for low cost 60 GHz radio applications is designed, modeled and analyzed. The results show a -10 dB impedance bandwidth of over 7 GHz with a radiation efficiency of over 95% making it suitable for short-range WPAN/WLAN applications. It is shown that two of the slot antennas can be configured orthogonally to achieve polarization diversity when fed separately. An isolation of at least 18 dB is obtained with an element spacing of ?/2. This can be advantageous for applications where the orientation of the terminal is not known.

Modeling of chip-package-PCB hierarchical power distribution network based on segmentation method

Abstract: In this paper, a new modeling method for fast estimation of impedance profile in system-level PDN containing not only chip, package and PCB-level PDNs but also various interconnections such as via, ball and bond-wire is proposed. The basic modeling method is segmentation method and FDTD based EM solver and a series of analytic modeling methods such as resonant cavity model and lumped circuit model are used. The proposed modeling method is successfully verified by measurement up to 20 GHz in frequency domain.

Estimation of parallel FDTD-based electromagnetic field solver on PC cluster with multi-core CPUs

Abstract: In this paper, the parallel and distributed FDTD (Finite-Difference Time-Domain) -based electromagnetic field solver is implemented on the PC cluster and multi-core CPUs system with MPI(message passing interface). In the FDTD method, the space including the object to be analyzed is divided to an enormous number of meshes. Although in general, the FDTD-based transient simulation is a time consuming task for the large scale space, FDTD method is a suitable technique for parallel computing because the electric and magnetic fields are updated with time progress using only adjacent electromagnetic variables. In this research, some electromagnetic simulations of the 2-D free space are performed by parallel computing method and the validity of this method is verified.

A frequency tunable resonant clock distribution scheme using bond-wire inductor

Abstract: In this paper, we propose a frequency control method for a resonant clock distribution scheme using a bond-wire inductor. The resonant clock distribution using the embedded planes in a package and an inductive load suppresses the clock source jitter and significantly reduces the clock skew by replacing the cascaded repeaters of a conventional on-chip clock distribution. The resonant frequency can be controlled by the inductance of the load and the size of cavity planes. We use a bond-wire inductor instead of a chip inductor for fine tuning of resonant frequency and reducing the parasitic capacitance of integration. We have successfully demonstrated a 1.35 GHz clock delivery network with the transmission line matrix model of the plane cavity and the lumped model of bond-wire inductor. The simulation results show that the source jitter is suppressed by the resonance effect and the skew is minimized and the frequency is controlled by the inductance of a bond wire.

Compact Electromagnetic Bandgap structure for noise suppression in power plane

Abstract: A compact reduced size new electromagnetic bandgap (EBG) structure with the combination of AIEBG and multiple narrow slits in power plane is presented. Low on-set frequency is realized by concatenating 2 × 2 high frequency unit cells into a low frequency EBG unit cell without changing the over all dimensions of the EBG. Newly designed EBG operates over a frequency band of 0.9 GHz to 3.5 GHz with a good isolation of better than -40 dB over the band with 2 × 2 unitcells. The impedance of the structure is also presented, which is less than one ohm over the stop band of the EBG. Both the simulation and the measured results are compared and presented.

Analysis of the EMI and SI effects on the flexible-PCBs for mobile application

Abstract: The irregular shape of Flexible Printed Circuit Boards (FPCBs) causes the EMI problem or unstable signal integrity that is the important factor to system performance. The FPCBs that is used the general mobile phone is modeled and simulated in this paper And it is analyzed about the EMI and signal integrity effects as the changes of the FPCBs? position and shape. The structure of the FPCB consists of a base film, copper foil and coverlay. Material of the base film and a coverlay is polymide and conductor uses copper. The FPCBs are modeled as the FPCBs? shape inserted in folder and slide type mobile phone. In the folder type, the length of modeled FPCB is 40 mm, and the slide type FPCB is 100 mm. And according to the each case, the statuses of the FPCB when the slide is closed and open are modeled. According to the results of simulation, the strength of electric field is maximum 488.31 V/meter as the shape of FPCBs. And there are the differences in signal integrity. For the folder type, the bended FPCB model has about 2.1 dB loss at 800 MHz. And there is 0.5 dB loss as the number of bended shapes in the slide type FPCB model. The consequence is that the bended shape can cause the EMI and signal integrity problem.

Implementation of HF/UHF multiband RFID reader SiP with Package-on-Package technology

Abstract: We have proposed a UHF/HF multi-band RFID reader, and we have implemented it into SiP with Package-on-Package technology. The proposed SiP RFID reader has been designed to support both for EPCgloabal Class1 Generation 2 protocol of UHF band, and 13.56 MHz RFID protocols of ISO14443 A/B type, and ISO15693 standards. The operating mode is controlled by embedded 32-bit RISC core, and the mode can be selected by users. The area of implemented SiP is 40 mm × 40 mm with 4 substrate layers. The implemented reader SiP operates at single supply voltage of 3.3V. The maximum current consumption is 210 mA. The measured operating distances are about 5cm for 13.56 MHz modes, and about 20 cm for UHF mode.

ASIC packaging challenges with high speed interfaces

Abstract: Networking speed is exploding as demanded with technology advancements and industry chip technology is evolving with rapidly increasing serial link data rates with high link integration for higher aggregate bandwidth and shrinking chip area and interface dimensions of devices. However, a large development speed gap between chip technologies and package technologies places great packaging challenges for high speed link applications where package wireability is driven by high frequency performance requirements. This paper discusses packaging challenges of high speed link applications with cost-performance tradeoffs in the technology trend.

Mode-impedance method for modeling and analysis of crosstalk in differential meander delay lines

Abstract: In this paper, the timing superposition method and the mode-impedance method have been proposed and verified by the TDR/TDT simulation for crosstalk analysis in differential transmission pairs. The modeled TDR/TDT waveforms in two cases by the mode-impedance method show a good correlation with the original TDR/TDT waveforms.

Signal integrity and reliability of a new Multi-Stack Package using a Pressure Conductive Rubber

Abstract: A proposed Pressure Conductive Rubber (PCR) is used instead of conventional interconnections such as wire and solder bondings for a Multi-Stack Package (MSP). A PCR for a three-dimensional (3-D) high-density interconnection has a major advantage in that it can replace defective dies with known good dies (KGD). In the structure of the PCR in this study working through external pressure, conductive particles are arranged between insulating rubber. To compare the RF electrical performance of the PCR and the solder interconnection, a test-jig with coplanar waveguide (CPW) was assembled. S-parameters and reliability tests of MSP formations using the PCR and solder interconnection were separately measured in a frequency range from 300 KHz to 8 GHz. The measured results show the insertion loss of 1.72 dB and the return loss of 12.7 dB on a single-layer structure at 8 GHz. Additionally, reliability tests of the PCR show stable electrical performance. These results indicate that the RF electrical performance of the PCR is acceptable for use in DDR3 SDRAM (Double Data Rate 3 Synchronous Dynamic Random Access Memory) applications.

Analysis of signal integrity/power integrity in multilayer printed circuit board and two improving methods

Abstract: The signal integrity (SI) and power integrity (PI) in multilayer printed circuit board is analyzed using three-dimensional (3D) full EM simulation and the circuit simulation. As a result of that, the dominant factor of SI/PI on the test board is noise coupling by GND via. Hence, two methods are applied to suppress the coupling; differential signaling and anti-via structure. Using these two methods, the noise on the signal line and power via can be suppressed, remarkably. Therefore, the SI/PI in multilayer PCB can be guaranteed to the low noise level.

Partial EBG placement on PDN to effectively suppress simultaneous switching noise

Abstract: To build a stable power distribution network (PDN) in high-speed digital systems, the simultaneous switching noise (SSN) should be sufficiently suppressed. In view of the results of recent research, the uni-planar compact electromagnetic bandgap (UC-EBG) structure is regarded as a promising solution to cope with the SSN problems until the GHz frequency ranges. However, if UC-EBG is adopted for the power/ground plane in the multilayer PCB/package structures, problems of signal integrity may result from the high speed signals passing over the EBG patterns because of the discontinuities of the etched reference plane. In this paper, the partial placement of EBG unit cells only near the sources of noise and/or the noise sensitive components is proposed as a means of both suppressing the noise propagation and minimizing the effects of a discontinuous reference plane. The SSN suppression performance of the proposed structure is validated and investigated both numerically and experimentally.

Pad shape effects on high frequency signal transfer characteristics

Abstract: As one of the interconnects between board to board, pads on the boards could have considerable effects on high frequency signal transfer characteristics. In this paper, pad shape effects on the signal integrity is analyzed using add-in card model by simulation, and a test fixture designed and fabricated to test to a serial-ATA cable is used to measure the effect of pad length on high frequency signal transfer characteristics. From the simulation and measurement, it is confirmed that the pads make a considerable effects on the signal transfer characteristics, especially in high frequency range, and we need to carefully design the characteristic impedance of the pads.