Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2010"

A dual-band filter using stepped-impedance resonator (SIR) embedded into substrate integrated waveguide (SIW)

Abstract: A new hybrid-integrated dual-band filter is proposed for WLAN application, where the lower passband is implemented by a pair of stepped-impedance resonators (SIRs) and the higher passband is provided by two substrate integrated waveguide (SIW) cavities. In our design, the SIRs are embedded into the SIWs to reduce the size. The relationship between the parasitic resonances of SIW structure and the locations of its transmission zeros is studied. Its good performances have been demonstrated by the simulated and measured S-parameters.

Performance analyse on millimetre-wave bonding-wire interconnection

Abstract: This paper presents a comprehensive analysis of the electrical performance of the bonding-wire interconnection up to 170 GHz. The effects of the wire length, loop height and pad area have all been analyzed. An electrical model for the bonding-wire is discussed. By reducing interconnection distance and optimizing pad area, the performance of the bonding-wire can be enhanced. The acceptable measurement results of the bonding-wire up to 170 GHz are obtained.

Conformal shielding investigation for SiP modules

Abstract: This paper proposes a complete testing process for conformal shielding techniques The testing process is systemic and cheap for developing conformal shielding techniques A 2-D experiment setup and an exact solution are presented to evaluate the properties of metals and metallization techniques A test vehicle is designed for providing broad band source and low unintended noise A experiment setup using giga-hertz transverse electromagnetic (GTEM) cell is proposed for providing low noise floor and high sensitivity for measuring small radiation The test vehicle coated by 004 μm sputtering SuS and 1 μm sputtering copper is manufactured and measured to evaluate shielding effectiveness of conformal shielding

Non-uniform currents on vias and their effects in a parallel-plate environment

Abstract: This paper discusses the generation of non-uniform currents on vias and their impact on the field distribution at the via antipads as well as on the excitation of cavity modes supported by adjacent reference planes. It is shown that the influence of non-uniform currents can be relevant at frequencies above 10 GHz for typical printed circuit board dimensions. The contour integral method is applied to extract the current non-uniformity due to vias in close proximity. An identification of modes is carried out via a discrete Fourier transform. The energy content of the higher modes increases with frequency and via size. It is demonstrated by means of full-wave simulations that non-uniform via currents can lead to anisotropic electromagnetic fields in the antipad region and to the excitation of anisotropic cavity modes.

Recent development of via models: Hybrid circuit and field analysis

Abstract: Via-plate interaction can be modeled as lumped circuits for vias and a two-dimensional field problem for the plate domain The accuracy of the improved intrinsic via model and the conventional physics-based via model is investigated by comparing them with either analytical formula or numerical simulations for a via in a circular plate pair with various edge boundary conditions It is found that the intrinsic via model matches very well with both the analytical formula and numerical solutions in all the examples studied However, the physics-based via model is only an acceptable approximation at low frequencies and its accuracy is not dependent on the plate size but on the via itself It is observed that the physics-based via model is more accurate for a plate par with smaller plate separations

Electrothermal modeling of coaxial through silicon via (TSV) for three-dimensional ICs

Abstract: An equivalent lumped-element circuit model of coaxial TSV is proposed in this paper, in which both frequency- and temperature-dependent elements are extracted using the partial-element equivalent-circuit (PEEC) method One important aspect of coaxial TSV modelling is its capacitance extraction, in which MOS effects are taken into account The circuit model is also reduced to a transmission line one, with its transmission characteristics predicted theoretically for the silicon material but with different resistivities

Hybrid modeling and analysis of power supply noise effects on analog-to-digital converter considering hierarchical PDNs

Abstract: An analog-to-digital converter (ADC) is an essential device in mixed mode systems. The performance of the ADC, however, is deteriorated by coupled power supply noises through hierarchical chip-PCB power distributed networks (PDNs). In order to design a high-performance system, modeling and analysis of power supply noise effects on the ADC are necessary, as the power supply noise is coupled to the circuit through the hierarchical PDN structure in multilayer PCB substrates. In this paper, a hybrid model is proposed for analysis of power supply noise effects on the ADC. The model combines two modeling mechanisms. First, the coupling ratio of the power supply noise is derived by the combined model of hierarchical PDNs at the PCB and the chip. Second, an analytical model is proposed using equivalent circuits for analysis of the power supply noise effects on the ADC. The ADC is designed using a 0.13um CMOS process. The proposed model and analysis are verified based on a simulation from 100kHz to 4GHz. The performance of the ADC is dominantly affected by characteristics of the on-chip circuit under 100MHz. It is also confirmed that the Effective Number of Bits (ENOB) of the ADC is strongly dependent on the hierarchical PDN impedance over 100MHz. Furthermore, there are peak points caused by inter-modulation (IMD) and cavity resonances of PDN structures.

Area-I/O RDL routing for chip-package codesign considering regional assignment

Abstract: Flip-Chip package provides high density I/Os and better performance in package size, signal/power integrety, and wirelength. Routing on its Re-Distribution Layer (RDL) is one of the most difficult stage in Flip-Chip packaging due to the increasing number of I/Os in modern VLSI designs. Area I/O can shorten the signal path and further increases the I/O density, but the design complexity is also higher. The Area I/O RDL routing problem is introduced in this paper, considering wirelength minimization and chip-package codesign. The proposed algorithm effectively solves the problem. 100% routability is guaranteed, from block ports to I/O pads and from I/O pads to bump pads. The authors propose the concept of regional assignment to evaluate the skew between bumps and balls. It leads the nets to route within neighbor sectors rather than the opposite sector. The experimental results, on 7 industrial designs, show that the router greatly minimizes bump-ball skew compared with [12], with reasonable extra wirelength.

A low-cost high-gain antenna array and its integration with active circuits

Abstract: At millimeter-wave frequencies, high-gain antenna and its integration with active circuits are of great concern. In this paper, a 2×4 antenna array is designed and fabricated on printed circuit board (PCB). At 135 GHz, the maximum gain is 15.4 dBi. It is much higher than that of a conventional on-chip antenna which is usually lower than −10 dBi. Subsequently, the low-cost wire-bonding technology is studied and adopted to integrate this array with active circuits.

Stub length prediction for back-drilled vias using a fast via tool

Abstract: This paper presents a fast via tool to predict the via stub length after back-drilling. The fast via tool is developed associated with the physics based via model and is combined with the calculation of plane impedance and via capacitance block by block. The entire via model is built by connecting those via blocks one after another accordingly. The plane impedance is calculated from an analytical formula and the via capacitance is computed from the point of view of energy by solving the potential distribution on each via block using FEM. Via stub length is predicted with the observation of strong resonant trough on the insertion loss, which can be in single-ended mode or mixed mode. Two cases, one signal via surrounded by eight ground vias and four signal vias surrounded by four ground vias, are used to verify the modelling accuracy of the fast via tool by correlating to the measurements. The third case is about via stub length extraction as well as the sensitivity investigation between the stub length and the resonant frequency.

Electrothermal modelling of through silicon via (TSV) interconnects

Abstract: Electrothermal effects in through silicon via (TSV) interconnects are investigated in this paper. The temperature-dependent TSV capacitance is calculated with MOS effect in silicon substrate considered. The per-unit-length resistance and inductance of TSV arrays made of different filling materials are extracted numerically with the partial-element equivalent-circuit (PEEC) method, and insertion losses of some TSV pairs are examined for different silicon substrate resistivities. The electrothermal responses of some TSV arrays made of different materials are also investigated using the modified time-domain finite-element method (TD-FEM).

On-chip PDN design effects on 3D stacked on-chip PDN impedance based on TSV interconnection

Abstract: This paper presents the analyses of 3D (3 Dimensional) stacked on-chip PDN (Power Distribution Network) impedances, which are composed with on-chip PDNs and TSV (Through Silicon Via) interconnections, and show the various features depending on on-chip PDN designs and 3D stacked chip configurations. Multi-stacked on-chip PDNs with very large capacitances interacting with even very small inductive TSV interconnections induces high PDN impedance peaks in GHz range, where single chip-PDN shows low PDN impedance. As multi-stacked on-chip PDN has larger capacitance, the high PDN impedance peaks appear at lower frequency range due to the relation of on-chip PDN capacitance and TSV inductance. Therefore, analysis and evaluation of on-chip PDN are very important to design 3D stacked chip. First, PDN impedance of single meshed type on-chip PDN is evaluated by the proposed on-chip PDN model and the measurement. Second, by using the evaluated on-chip PDN impedances and simple inductor model of TSV, the PDN impedances of 3D stacked on-chip PDNs is analyzed in consideration with the various on-chip PDN designs and stacked on-chip PDN numbers.

Design and simulation of a compact novel LTCC antenna for integrated Bluetooth applications

Abstract: A compact novel antenna for Bluetooth or wireless LAN applications by low-temperature co-fired ceramic (LTCC) tochnology is presented in this paper. The novel antenna is composed of stacked meander, helix structures, and multi-layer parasitic patches are employed to miniaturize the antenna. The simulated results show that the proposed antenna, having compact size of 3.2×1.6×1.2mm3, has a bandwidth of 60MHZ (VSWR<3:1) and a maximum gain of 0.5dBi, realizes omnidirectional radiation patterns across the whole operating frequency band.

A new methodology for IC-package thermal co-analysis in 3D IC environment

Abstract: Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology to accurately and efficiently predict power and temperature distribution for 3D ICs.

Power noise suppression techniques using spiral resonator in high-speed PCB

Abstract: In this paper, to the aim of more than 10 dB power noise suppression, investigation of spiral resonators applied in the vicinity of the practical high-speed digital circuit. Their performances are characterized in terms of their capability to effectively suppress simultaneous switching noise in the frequency region of interest with small occupying area on the power distribution network. As a starting point, the maximum order of harmonic up to which the most energy of clock signal is concentrated is estimated by power spectrum analysis for practical high-speed digital circuit. Then, design parameters of a spiral resonator such as the width, the gap and the number of turns were simulated to determine the suppression level and bandwitdh in DDR3 signal. Numerical results are given in order to illustrate the effectiveness of noise suppression of spiral resonator and to validate the theoretical analysis.

RF substrates yield improvement using package-chip co-design and on-chip calibration

Abstract: In this paper, yield improvement methodology is proposed for RF substrates with embedded RF passive circuitry. The proposed methodology introduces a concept of package-chip co-design and on-chip calibration of active circuitry for the yield improvement of off-chip passive embedded RF filters. RF receiver architecture for the package-chip co-design and on-chip calibration technique is presented. Using the proposed methodology, it is shown that the yield of RF substrates is improved from 88% to 98%. Also, the measurements results are presented.

Controllable slow-wave delay line

Abstract: On-chip transmission lines are basic components in millimeter-wave and terahertz circuits. In this paper, slow-wave CPW with a simple mosfet switch, ie. controllable slow-wave CPW as a controllable phase delay line are designed, characterized and analyzed in a commercial 0.18μm CMOS process. Based on measured two-port S-parameters up to 110GHz, the phase constants are compared at variation of the bias. It shows a continuously 15° delay over frequency range of 63 GHz to 98 GHz with a minimum insertion loss of 3.2 dB and a maximum insertion loss of 5.5 dB.

Bandwidth and density reduction of tabulated data using causality checking

Abstract: A canonical interconnect model is studied to determine metrics for bandwidth and data density minimization using a causality checker for validation It is found that insertion loss roll off to −30dB and logarithmic data spacing with 11 factor spacing interval preserves good causality checker error Wide bandwidth is needed for the causality check even for low bandwidth applications

Evaluation of IBIS modelling techniques for signal integrity simulations without and with package parasitics

Abstract: Input/Output Buffer Information Specification (IBIS) models are widely used in signal integrity analysis because of their ability to protect proprietary information and to reduce simulation time when compared to full SPICE simulations Generation of IBIS models with I/V and V/T data from a full SPICE model of a typical digital buffer without and with package parasitics is investigated in this paper Several different IBIS model generation strategies to incorporate package effects are validated with the full SPICE model in order to provide a suitable approach In addition, the accuracy of IBIS simulations in HSPICE and ADS is investigated

Jump the Q: A fast jitter tolerance measurement method using Q-statistical model

Abstract: With high-speed receivers and clock data recovery (CDR) blocks operating at speeds in excess of 10 Gbps, stringent CDR jitter tolerance test criteria are necessary to qualify device reliability A robust CDR jitter tolerance test should accommodate test criteria with extremely low bit error rate (BER) values, usually 10−12 or lower for typical industrial protocols Using conventional methods, the time required to measure a complete set of CDR jitter tolerance values can stretch into weeks depending on the data rate In general, measurement time increases tenfold for a similar tenfold reduction in BER This translates to prohibitively long measurement times for BER values of 10−15 and lower Statistical extrapolation for low BER measurement such as Q scale has been widely used in the industry, but this is only applied for transmitter measurements, specifically jitter measurements This paper introduces a novel, fast measurement method for receiver testing based on the Q-statistical method to predict the BER for high-volume data transmission based on small sample data sets Experimental data using this method show that extrapolated jitter tolerance values for BER values down to 10−15 can achieve an accuracy of 125 mUI This innovative method improves the efficiency of jitter tolerance tests by significantly reducing measurement time Furthermore, the method allows for the extension of measurement scope to cover previously unattainable jitter tolerance values for lower BER values With these advantages, full jitter tolerance characterization on Altera Stratix® IV GX devices successfully meets very aggressive product rollout and time-to-market schedule, even with measurements for 24 protocols and support for BER of 10−12 and lower

Power supply noise evaluation with on-chip noise monitoring for various decoupling schemes of SiP

Abstract: Power integrity design is a critical issue in system-in-packages (SiP's). In particular, power supply disturbance excited by simultaneous switching output (SSO) noise, or core circuits is serious in a 3D stacked die packages. Therefore, decoupling schemes in such SiP's must be carefully designed to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range and to avoid the parallel resonance occurred by chip-package connection. In this paper, a test chip was designed and fabricated to generate noise and to monitor on-chip power supply noise. Then, a power noise evaluation system has been established. Power supply noise on core circuits was measured with a noise monitoring circuit. The noise on output buffer circuit was measured by a fixed high/low method. Power supply noises were examined in various decoupling schemes. They are with embedded SMD capacitors inside interposer, and SMD capacitors mounted on the backside of interposer along with on-chip capacitance.

Augmented EPA with augmented EFIE method for packaging analysis

Abstract: It is evident that the low frequency full wave electromagnetic modelling is necessary for IC packaging analysis Considering the complexity, it is very difficult to solve the whole problem directly Even though the domain decomposition method is a legitimate approach for these types of problems, the domain decomposition method based on the equivalence principle has the low frequency breakdown issue In this paper, we developed a low frequency augmented equivalence principle algorithm (AEPA) with the augmented electric field integral equation (AEFIE) for packaging and IC analysis On the equivalence surfaces, not only the electric current and the magnetic current, but also the electric charge and the magnetic charge are used to capture the low frequency couplings Inside each AEPA box, AEFIE is applied to maintain the low frequency accuracy As a result, we are able to solve low frequency domain decomposition problems and apply it to IC packaging analysis

A tri-band filter using tri-mode stub-loaded resonators (SLRs)

Abstract: The tri-mode stub-loaded resonators (SLRs) are employed in the design of a tri-band bandpass filter (BPF), where a special coupling structure is used to provide enough design freedom, and a magnetic source-load coupling is introduced to improve the frequency selectivity with six transmission zeros The good performance of our proposed filter is demonstrated by good agreement obtained between the simulated and measured S-parameters

Design of toroidal current probe embedded in multi-layer printed circuit boards for electrostatic discharge(ESD) detection

Abstract: In this paper, we propose a novel toroidal current probe embedded in multi-layer printed circuit boards (PCBs) for electrostatic discharge (ESD) detection The proposed current probe consists of an inner via-array, bridge lines, and an outer via-array, which surround an ESD current path and form a toroid to detect an ESD current A transfer impedance between a port injected an ESD current and the proposed current probe is used for analysis of an ESD current coupling Through experimental measurements, we verified the proposed current probe by comparison with a conventional current probe

Neural network techniques for fast parametric modeling of vias on multilayered circuit packages

Abstract: This paper provides an overview of recent advances of neural network techniques for fast and parametric modeling of vias on the multilayered circuit packages First, we review a space-mapping neural network technique for broadband and completely parametric modeling of vias This technique exploits the merits of space-mapping technology and incorporates an equivalent circuit into the model structure The neural network is trained to learn the multi-dimensional mapping between the geometrical variables and the values of independent circuit elements in the equivalent circuit Once trained with the EM data, this model provides accurate and fast prediction of the EM behavior of vias with geometry parameters as variables We also review a combined neural networks and transfer functions technique for via modeling This technique is capable of providing accurate simulation models even if an equivalent circuit is not available It retains the EM level accuracy and reduces CPU time significantly compared to EM simulator Experiments in comparison with measurement data and EM simulations are included to demonstrate the merits of these neural network techniques

Chip-package-board co-design for complex System-on-Chip (SoC)

Abstract: Device scaling has allowed us to pack more functionality in a smaller die area The ever increasing number of interfaces and the complexity of advanced SoCs force custom package design for almost every device rather than using a standard of the shelf package The time-to-market window is shrinking with rapidly growing demand in the consumer market To meet package performance with reduced package size and cost constraints, early evaluation of package and board routing is required Floorplan of today's complex SoCs' is driven not only by the package but also board and overall system design Chip-Package-Board co-design is obligatory to meet performance and schedule requirements as well as to reduce the system cost This paper talks about the co-design challenges on a 40nm complex SoC implementation

Design of TEM cell and high sensitive probe for EMI analysis of built-in Webcam module

Abstract: Since many extremely susceptible components with low-voltage operation or high sensitivity may be affected from EMI noise and thus degrade their performance, the EMI phenomena from IC becomes an issue for semiconductor industry In this paper, we have designed a TEM Cell and magnetic field probe with high sensitivity and spatial resolution, in accordance with the IC-EMI measurement standard IEC 61967–2 [1] and IEC 61967–3 [2] respectively The goal is to setup a more accurate measurement of the noise source location and the corresponding frequency bands to analyze the platform noise effect The operating frequency of TEM Cell has been raised up to 243 GHz Two identical IC for Webcam module with some minor modifications were used for EMI measurement and further analysis for the interference effects

FdSPICE: A parallel simulation technique for lossy and dispersive interconnect networks

Abstract: This paper presents a parallel algorithm for the simulation of large complex interconnect networks with frequency-dependent parameters. The equivalent transmission line model, which is suitable for time-domain simulation, is introduced for the modeling of dispersive interconnects. By means of the equivalent multi-port model, the interconnects are separated from other circuit elements, and thus makes the parallel simulation feasible. Based on the proposed technique, a program named FdSPICE is developed for parallel simulation of large interconnect networks. The accuracy and efficiency of FdSPICE are demonstrated by numerical examples.

Comparing flip-chip and wire-bond package effects on a receiver low-noise amplifier

Abstract: A comprehensive study based on chip-package co-modeling compares the effects between flip-chip ball-grid-array (FC-BGA) and wire-bond quad-flat-nonlead (WB-QFN) packages on a front-end cascode low-noise amplifier (LNA) in a 245 GHz CMOS wireless local area network (WLAN) receiver In practical applications, the established package models are used to predict the degradation of figure of merit (FOM) for the cascode LNA under packaged condition Chip-package co-modeling results achieve good agreement with measurements, and thus can persuasively account for the complete effects caused by the two different packages on the cascode LNA

Study of high speed interconnects of multiple dies stack structure with Through-Silicon-Via (TSV)

Abstract: Die stacking is widely adopted for high chip count systems to reduce the requirement of substrate area The incorporation of Through-Silicon-Via (TSV) as vertical interconnects further reduces the interconnect path length from the top die to substrate As the fabrication resolution keeps on shrinking, devices of even higher chip count are required to be assembled in a single package, which results in even longer 3D interconnects As such, accurate modelling of high speed interconnects is essential for the high frequency systems In this work, 3D modelling and Full wave EM simulation were performed on the interconnect path which consists of TSV, metal re-distribution Layer (RDL) and bumps Effect of the different number of die stack was analyzed based on the simulation results