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Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2012"


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, signal integrity analyses of single and multi-layered GNR (SLGNR and MLGNR) interconnects are carried out based on their equivalent circuit models, with crosstalk effects characterized theoretically.
Abstract: Graphene nano-ribbons (GNR) have been proposed for building up interconnects for 3-D ICs, due to their superior performance over conventional metallic materials In this paper, signal integrity analyses of single- and multi-layered GNR (SLGNR & MLGNR) interconnects are carried out based on their equivalent circuit models, with crosstalk effects characterized theoretically It is shown that longer length and larger width of the SLGNR interconnect will result in higher crosstalk voltage, but it cannot exceeds its threshold one While for MLGNRs, their advantages over Cu wires are kept even with the worst crosstalk

19 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, slow-wave sections are utilized for the inner line to compensate the length difference from the outer one to suppress the differential-to-common mode conversion of bend discontinuity for differential signaling.
Abstract: A new method is proposed to suppress the differential-to-common mode conversion of bend discontinuity for differential signaling. Slow-wave sections are utilized for the inner line to compensate the length difference from the outer one. By properly selecting the geometry, a significant reduction of 87.5% can be achieved for the time-domain differential-to-common mode transmission response while the magnitudes of differential-mode and differential-to-common mode reflections are kept small. The differential-mode transmission is improved by 4 dB at 10 GHz. The method has been demonstrated by the simulated and measured results of the fabricated prototype.

16 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: All the three steps required for implementing the M3-approach are illustrated for bond wire antennas and reliable design measures are derived.
Abstract: In this paper, all the three steps required for implementing the M3-approach are illustrated for bond wire antennas. First, a methodology for efficient and accurate electromagnetic modeling of bond wire antennas, based on parameterized models of the shape and length of bond wires, is developed. The resulting model is experimentally verified and applied to extensively study the RF performance of bond wire antennas. Based on these studies, reliable design measures are derived.

12 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, a novel equivalent circuit model of through-silicon via (TSV) considering the time-dependent capacitance due to metal-oxide-semiconductor (MOS) effect has been proposed.
Abstract: A novel equivalent circuit model of through-silicon via (TSV) considering the time-dependent capacitance due to metal-oxide-semiconductor (MOS) effect has been proposed. This model can characterize the variance of capacitance between metal and silicon substrate caused by the differential change of depletion region width as the voltage applied on the TSV changes with time. Compared to conventional TSV models, the capacitance has a 70% difference when the TSV's applied voltage transits from low state to high state. Besides, 3% difference of eye height and 100% difference of eye jitter can be observed in eye diagram by SPICE simulation.

12 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, the simulation results of substrate noise coupling between through silicon via (TSV) and MOSFET were presented and discussed through 2D and 3D transient analyses, and noise isolation methods including guard rings and grounded shield TSV were incorporated to improve the noise decoupling.
Abstract: This paper presents simulation results of substrate noise coupling between through silicon via (TSV) and MOSFET. Electrical noise coupling through coexistence of junction capacitances and threshold modulation in substrate is studied and discussed through 2D and 3D transient analyses in this paper. Furthermore, noise isolation methods including guard rings and grounded shield TSV are incorporated to improve the noise decoupling and are examined to verify their effectiveness.

11 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, the effect of depletion region formed by a DC bias voltage was considered and an extended capacitance matrix equation was obtained to include depletion capacitances, and the new formula was inserted to the original formulation.
Abstract: TSV modeling method based on cylindrical modal basis functions is modified to consider the effect of depletion region formed by a DC bias voltage. Extended capacitance matrix equation is obtained to include depletion capacitances, and the new formula is inserted to the original formulation. The proposed method is tested for two TSVs with varying depletion depths, and the computed insertion losses, capacitance, and conductance show reasonable trends.

10 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the authors investigated how open via stubs in multilayer printed circuit boards (PCBs) affect the time-domain transmission (TDT) waveform and eye diagram.
Abstract: Plated though-hole (PTH) vias are extensively adopted in multilayer printed circuit boards (PCBs). Unused portions of PTH vias become open stubs, which excite the resonance mode and degrade signal integrity (SI). This work investigates how open via stubs in multilayer PCBs affect the time-domain transmission (TDT) waveform and eye diagram. Exactly how time-domain reflection affects the open via stubs on TDT waveform is also studied using the lattice diagram. Additionally, the R and RL terminations of open via stubs are developed to improve SI in previous studies. Moreover, the RC termination of open via stubs is proposed to improve the performance of SI, which is the same as that of the R termination in this work. RC termination is also characterized by its nearly zero DC power consumption. Furthermore, different terminations are compared with respect to how they improve the TDT waveforms and eye diagrams.

10 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the authors compared the characteristics and limitations of a 4-element linear model of a voltage regulator module by comparing it with a state average model (SAM) with feedback used by Intel.
Abstract: This paper discusses the characteristics and limitations of a 4-element linear model of a voltage regulator module (VRM) by comparing it with a state average model (SAM) with feedback used by Intel. A virtual load line method is proposed to correlate the 4-element linear model by introducing a modified DC resistance. The resultant impedance profile is in good agreement up to 2GHz with that by original SAM. Furthermore, it can be simplified to a 2-element model, which still gives good agreement since the high frequency impedance is dominated by the bulk capacitance in realistic PDN's.

8 citations


Proceedings ArticleDOI
Do-Young Jung1, Joohee Kim1, Heegon Kim1, Joung-Keun Kim1, Joungho Kim1, Jun So Pak1 
01 Dec 2012
TL;DR: In this paper, a gap between a TSV and the corresponding bump is calculated to analyse its effect on the system; the calculated values for 1 μm, 3 μm and 5 μm gap resulted in 14.07 fF, 4.69 fF and 2.82 fF respectively.
Abstract: The trend in semiconductor industry is rapidly shifting from 2-dimension to 3-dimension to satisfy the ever-growing demand on the miniaturization of electronic devices. The introduction of through silicon via (TSV) based 3-dimensional integrated circuit (3D-IC) has significantly advanced the technology to realize high speed system with increased functionality. However, challenges remain in reliability of fabrication and testing methods. The size of transistors and interconnections has shrunk to few tens of nanometers, requiring highly advanced technique in the fabrication process. The precision in existing fabrication process is insufficient to reach the acceptable level of chip yield. Thus, TSV failure detection and analysis is essential for 3D-IC technology. One of the main failures that degrades the chip performance is disconnection failure. Disconnection failure may form in any point along the channel, especially in between the stacked layers. Stacked dies with TSVs as interconnects can be analysed by equivalent circuit model. Each component is represented as lumped components according to its material and physical dimensions. A disconnection along the channel is a gap between two conducting materials, which is modelled as series capacitance. The gap between a TSV and the corresponding bump is calculated to analyse its effect on the system; the calculated values for 1 μm, 3 μm and 5 μm gap resulted in 14.07 fF, 4.69 fF, and 2.82 fF, respectively. The modelled components were inserted and S-parameter plots were extracted for analysis.

8 citations


Proceedings ArticleDOI
Joung-Keun Kim1, Heegon Kim1, Sukjin Kim1, Changhyun Cho1, Do-Young Jung1, Joungho Kim1, Jun So Pak1 
01 Dec 2012
TL;DR: In this article, the authors proposed a contactless wafer-level TSV connectivity testing structure that can detect TSV defects on wafer level, while overcoming the limitations of the conventional direct probing method.
Abstract: With the advent of 3D-IC, Through Silicon Via (TSV) has been highlighted as the key technology for compactly integrating dies of various functions. However, due to the instability in the TSV fabrication process, various types of failure can be resulted, resulting in drastic decrease in the final chip yield with the increase in the number of TSVs and stacked dies. In this paper, we propose a novel contactless wafer-level TSV connectivity testing structure that can detect TSV defects on wafer-level, while overcoming the limitations of the conventional direct probing method. TSVs are aligned and connected as to enable the detection of change in the series capacitance between adjacent TSVs for verification of the TSV defects. Through time- and frequency-domain simulation results, we verified that the proposed structure can successfully detect TSV defects.

7 citations


Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the authors present an advanced test methodology to evaluate in-the-band leakage of out-of-band undesired frequencies using an anechoic chamber as test facility and using multiple-tone excitation from a dual-source network analyzer.
Abstract: In low-cost miniaturized electronic systems, filters are often omitted in front of active non-linear components, potentially resulting in unwanted intermodulation products in the band of operation. Current immunity tests most often use a single-frequency source and are hence not able to capture all relevant intermodulation products. Relying on an anechoic chamber as test facility and using multiple-tone excitation from a dual-source network analyzer, we present an advanced test methodology to evaluate in-the-band leakage of out-of-band undesired frequencies. To demonstrate our approach we use a frequency-selective active textile antenna with integrated non-linear low-noise amplifier.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: The example of a 6 gigabit per second SAS interface is used to illustrate the proposed simulation method of combining an empirical and analytical approach to estimate the effects of inter-symbol interference (ISI) and channel jitter using an IBIS-AMI models.
Abstract: High-end, high-performance computers use high-speed serial interfaces to pass data and control signals between the electronic components in the systems These interfaces include proprietary interfaces unique to a class of systems and some interfaces, such as PCIe & SAS, which have publicly available standards and specifications that enable communication between electronic components from different manufactures The IBIS-AMI model has been developed to facilitate circuit simulation of high-speed serial interfaces and is particularly useful in simulating communication between transmitters and receivers procured from different manufactures The simulations are performed to ensure that the interface specifications are met, including the eye characteristics, and that the bit error rate (BER) is less than a specified maximum There are many variables and long bit strings needed to predict a BER of sufficiently low amplitude Therefore, an efficient and accurate estimation of BER requires significantly long simulations times In this paper, we use the example of a 6 gigabit per second (Gb/s) SAS interface to illustrate our proposed simulation method of combining an empirical and analytical approach to estimate the effects of inter-symbol interference (ISI) and channel jitter using an IBIS-AMI models

Proceedings ArticleDOI
Jun So Pak1, Joohee Kim1, Do-Young Jung1, Jun Ho Lee2, Kunwoo Park2, Joungho Kim1 
01 Dec 2012
TL;DR: In this article, an optimization of inverter design for ring oscillator based wafer-level TSV connectivity test (RO-TSV-CT) scheme is proposed, which contains many inverters, is located to TSVs and input/output circuitries (I/Os) very closely.
Abstract: Optimization of inverter design for ring oscillator based wafer-level TSV connectivity test (RO-TSV-CT) scheme is proposed. Since RO-TSV-CT is based on ring oscillator, it contains many inverters, is located to TSVs and input/output circuitries (I/Os) very closely. Therefore the inverters should be designed so as not to consume on-chip I/O design area, not to have complex power supply network, and not to give parasitic capacitance loading to I/Os. Especially, it should give a very effective and accurate test result. This paper shows the optimization results based on TSMC 0.18 um technology.

Proceedings ArticleDOI
Sven Kuehn1, M. Wild, P. Sepan, E. Grobelaar, Niels Kuster1 
01 Dec 2012
TL;DR: In this paper, the authors present an automated near-field scanner for chip-level EMC/EMI evaluations in the RF domain, which combines a large scanning volume of 500×500×100mm3 with micrometre resolution.
Abstract: We present an automated near-field scanner for system- to chip-level EMC/EMI evaluations in the RF domain. The scanning system combines a large scanning volume of 500×500×100mm3 with micrometre resolution. A novel optical surface reconstruction system allows measurement of the height map of the device under (DUT) test with better than 20μm uncertainty. This allows scanning at a precise distance above arbitrary electronic components. Key components of the scanning system are novel active miniaturized electro-optical time-domain E- and H-field sensors in the frequency range from 0.01 to >6GHz measuring the complex amplitude with a dynamic range of >120dB. The full optical isolation of the probes eliminates disturbance of the field of the DUT compared to electrically connected probes and offers up to 60dB better sensitivity than passive electro-optical probes.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the authors present the use of a design flow and remarkable results of signal integrity crosstalk simulations of multi-GigaHertz serial links in high density printed circuit boards, which becomes mandatory due to increase of data rates.
Abstract: This study presents the use of a design flow and remarkable results of signal integrity crosstalk simulations of Multi-GigaHertz serial links in high density printed circuit boards, which becomes mandatory due to increase of data rates

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure was analyzed.
Abstract: The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc) Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc) Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak

Proceedings ArticleDOI
01 Dec 2012
TL;DR: This paper designs and fabricates an STL prototype, and demonstrates that the eye-diagram distorted in the lossy transmission line is improved dramatically more than twice in its eye-height in the STL.
Abstract: Waveform distortion in lossy transmission lines is getting serious in long traces in PCBs in GHz domain. So far this signal-integrity (SI) degradation problem has been solved with some active devices, such as equalizer, pre-emphasizer or de-emphasizer. These devices however require unnecessary power-consumption, cost, and packaging area. We have proposed a novel PCB trace structure called “Segmental Transmission Line (STL)” already in order to reduce reflection noises in the bus wires. In this paper, we firstly apply the STL to restore the waveforms distorted in the lossy transmission line without the active devices. We design and fabricate an STL prototype, and demonstrate that the eye-diagram distorted in the lossy transmission line is improved dramatically more than twice in its eye-height in the STL.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, the impact of TSV induced stress on nMOSFET performance is insignificant compared to that of tensile stress liner in the device and the interaction between TSV, stressors such as tensile stressed liner and Shallow Trench Isolation (STI) and device channel is considered.
Abstract: Evaluation of the impact caused by Through-Silicon Vias (TSV) induced thermo-mechanical stress on device performance is becoming important due to the close proximity between TSVs and the semiconductor devices in 3D integration From the literatures, there exist discrepancies between theory, simulated and experimental results presented For accurate predictions, we simulated stress build-up by taking the full CMOS process flow into consideration We considered the interaction between TSV, stressors such as tensile stress liner and Shallow Trench Isolation (STI) and device channel From the results, it was found that the nMOSFET Ion variation is less than 2% at Keep Out Zone (KOZ) of 1 μm due to TSV induced stress while the Ion variation is about 30% due to the tensile stress liner Hence, the impact of TSV induced stress on nMOSFET performance is insignificant compared to that of tensile stress liner in the device

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, an on-chip embedded current probe that uses magnetic field coupling mechanism to determine onchip switching current waveform especially in chip I/O power distribution network (PDN) is presented.
Abstract: In this paper, we present an on-chip embedded current probe that uses magnetic field coupling mechanism to determine on-chip switching current waveform especially in chip I/O power distribution network (PDN). We first investigate the characteristics of magnetic coupling behaviour of proposed on-chip current probing structure in various geometrical design parameters like metal width and ratio of winding turns. And then we explain our current waveform reconstruction technique which is based on time and frequency domain measurement data of our proposed on-chip current probe including magnetically induced voltage measured in time domain and transfer impedance measured in frequency domain. Numerical simulation results and experimental measurement results are shown to demonstrate the magnetic coupling behaviour of our on-chip embedded current probes which are designed using a Samsung 0.13um CMOS process.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, an example is given by simulation and measurement that the IO cable radiation can be from the intentional differential-mode signals, which explains why populating common mode chokes to mitigate radiation is not effective.
Abstract: IO cable radiation is believed to be mainly from the unintentional common-mode signals transmitting on the differential lines. In this paper, an example is given by simulation and measurement that the IO cable radiation can be from the intentional differential-mode signals. This explains why populating common mode chokes to mitigate radiation is not effective.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, an on-board snubber (RC series circuit) was investigated to improve power supply integrity in a FPGA (Field Programmable Gate Array) board.
Abstract: Simultaneous switching noise (SSN) is a serious design issue to stabilize logic operation and to reduce electromagnetic interference (EMI) in advanced CMOS circuits and systems. Ringing frequency observed in the SSN waveforms is strongly related to the anti-resonance peak frequency of total PDN impedance. In this paper, on-board snubber (RC series circuit) was investigated to improve power supply integrity in a FPGA (Field Programmable Gate Array) board. The on-board snubber circuits was added just at the beneath of the power supply terminals of the FPGA to effectively suppress the anti-resonance peak of the total PDN impedance. Design space to damp the anti-resonance peak was examined. In particular, the values of on-board capacitance and resistance of snubber circuit has been examined by using circuit analysis tool and field solver.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, the fundamental principles and properties of the electromagnetic radiations caused by vias and traces in IC packagings are investigated and various radiation mechanisms are analyzed for different representative scenarios.
Abstract: The EMC and EMI of the IC packaging are becoming increasingly important to modern electronics. Its EMC, SI, and PI have been broadly attested. But electromagnetic radiations from IC packaging and the corresponding EMI were seldom studied. In this paper, the fundamental principles and properties of the electromagnetic radiations caused by vias and traces in IC packagings are carefully investigated. Various radiation mechanisms are analyzed for different representative scenarios. Numerical simulations are employed to support the analyzing results.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: This paper proposes a locally implicit latency insertion method (LILIM), which is a suitable method for the fast simulation of an arbitrary shaped power distribution network (PDN) modeled by triangular meshes by combining the efficient modeling and the locally implicit schemes.
Abstract: This paper proposes a locally implicit latency insertion method (LILIM), which is a suitable method for the fast simulation of an arbitrary shaped power distribution network (PDN) modeled by triangular meshes. First, an efficient modeling method based on triangular mesh is reviewed and we refer to the limitation of the LIM for the meshed PDN analysis. Next, in order to overcome the problem, we formulate the LILIM by combining the efficient modeling and the locally implicit schemes. Finally, the numerical results show that the LILIM is applicable and efficient for the simulation of the PDN analysis.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, a bended differential transmission line using the balanced model is proposed to efficiently reduce the common-mode noise, which can greatly reduce the mode conversion from ™5.47 dB to ™14.86 dB.
Abstract: In this paper, a bended differential transmission line using the balanced model is proposed to efficiently reduce the common-mode noise. The bended differential transmission line using the balanced model can greatly reduce the mode conversion from ™5.47 dB to ™14.86 dB and the TDT common-mode noise from 0.068 V to 0.023 V as compared with the bended differential transmission line using the right-angle bend. In order to verify the simulation results, measurement is done in the frequency and time domains where the measurement results are in good agreement with the simulation results.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, a detailed mathematical analysis that employs transmission line theory along with the imbalance model is presented and the validity of the model is extended to a higher frequency range, under certain operating conditions.
Abstract: Common-mode current traveling on peripheral cables can be a major source of radiated emissions and a potential electromagnetic compatibility (EMC) hazard Models and tools for early prediction of common-mode current proved extremely useful for EMC engineers Imbalance difference model has been one the most successful common-mode modeling techniques in EMC literature It has, however, been only validated at the low EMC frequency range below 1 GHz In this work, detailed mathematical analysis that employs transmission line theory along with the imbalance model is presented The limitations of the imbalance model are explored and discussed The validity of the model is extended to a higher frequency range, under certain operating conditions Finally, closed-form expressions for estimating common-mode electric-field are introduced, offering the possibility of replacing complex full-wave simulations

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, a direct probe interface is applied to the post-bond probe in 3D ICs to improve the test reliability and reduce the test cost in the whole test flow.
Abstract: Three-dimensional integrated circuit (3DIC) technologies with the vertical stacking schemes offer the promising performances but are sensitive to the post-bond probe in the testing reliability. In order to overcome this test challenge, the direct probe interface is applied and the performances of chip are also demonstrated. By using the direct probe interface, the post-bond chips have gained with 48% bandwidth enhancement and the test cost is also reduced in the whole test flow due to the reusable characteristics.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, an explicit and unconditionally stable finite difference scheme in which the constraint of time step size is overcome by removing the unstable modes has been proposed to perform the fast transient simulation of power distribution networks with extremely small apertures.
Abstract: Generally, an explicit difference scheme has the numerical stability condition which constrains the time step size, and this condition depends on the lowest reactance component If the time step size that does not fulfill the numerical stability condition is used, unstable modes arise, and we fail the transient analysis In this paper, we propose an explicit and unconditionally stable finite difference scheme in which the constraint of time step size is overcome by removing the unstable modes Numerical results show that the proposed method is quite effective to perform the fast transient simulation of power distribution networks with extremely small apertures

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, an efficient method based on the equivalent single conductor (ESC) model and delay extraction technique is presented to investigate the crosstalk effects of complex multi-walled carbon nanotube (MWCNT) interconnects.
Abstract: In this paper, an efficient method based on the equivalent single conductor (ESC) model and delay extraction technique is presented to investigate the crosstalk effects of complex multi-walled carbon nanotube (MWCNT) interconnects Each MWCNT interconnect is first characterized by the ESC model A decoupling algorithm is then utilized to transform the coupled interconnects into a set of individual lines After that, based on a modified Lie formula, a delay algebraic equation is derived to obtain the time domain response of each single interconnect The validity and efficiency of the proposed method are demonstrated by the numerical example and compared with the original multiconductor circuit (MCC) model Some discussions on the numerical results of crosstalk effects obtained by the two models are also given

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this paper, measurements are made to validate the electrical performance of a Through Silicon Via (TSV) interconnection up to 40GHz, and the results of the wideband scalable model of TSV is proposed and compared with the measured data.
Abstract: In this study, measurements are made to validate the electrical performance of a Through Silicon Via (TSV) interconnection up to 40GHz, and the results of the wideband scalable model of TSV is proposed and compared with the measured data. Measurement of the TSV structure demonstrates its advantages of low parasitic capacitance and low insertion loss at high frequency.

Proceedings ArticleDOI
Manho Lee1, Jonghyun Cho1, Joungho Kim1
01 Dec 2012
TL;DR: In this article, the authors investigated the noise coupling between signal TSV and active circuit in frequency domain using 3D EM solver and found that the active circuits and TSV are generally surrounded by deep N-well and substrate ties, some parameters related to dimension parameters of those are varied to clarify the tendency.
Abstract: This paper investigates about the noise coupling between signal TSV and active circuit in frequency domain using 3D EM solver Because the active circuits and TSV are generally surrounded by deep N-well and substrate ties, some parameters related to dimension parameters of those are varied to clarify the tendency, and the results are explained qualitatively After that, using S-parameter, simple MOS application is simulated in time domain simulation