Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2014"

Silicon-package power delivery co-simulation with Fully Integrated Voltage Regulators on microprocessors

Abstract: Fully Integrated Voltage Regulator (FIVR) has been introduced on Intel® Xeon® microprocessors which are switching power converters on die. The FIVR design includes air core inductor structures implemented on the package along with output capacitor, compensators, power transistors and control circuits implemented on-die. FIVR analysis has to comprehend and co-optimize both the package and the die. The power delivery analysis of FIVR is presented and design optimizations are discussed.

A novel wideband common-mode suppression filter for differential signal transmission

Abstract: A novel wideband filter is designed for common mode noise (CMN) suppression in high-speed differential signaling. The dumbbell-shaped defected ground structure (DGS) is periodically etched in the return path of differential line to suppress CMN. In order to improve the signal quality of the differential transmission, a periodic stub-loaded structure is designed to compensate the discontinuity of the odd-mode characteristic impedance. Furthermore, a slow-wave structure is employed to decrease the Bragg frequency and then enhance the bandwidth of CMN suppression effectively without enlarging the circuit size. The simulated and measured results of the prototype indicate that the CMN can be suppressed over 20 dB from 3.2 to 8.6 GHz by the filter, while good transmission characteristic can be achieved for the differential signals.

Design and analysis for noise suppression of DC/DC converter

Abstract: DC/DC converters are widely used to provide various power supply voltages required for many electronic components on a board Though DC/DC converter is more efficient than the linear regulator is, however, the switching noise becomes larger with the increase of the switching frequency In particular, ringing noises at the sharp rising edge of the switching waveform occurs by the effect of the parasitic inductance of trace pattern Then, this noise spreads out to the whole circuit board, and generates electromagnetic interference (EMI), which often causes a malfunction of the other electronic systems In this paper, the methods to accurately reproduce the switching waveforms and to reduce ringing noises were investigated For this purpose, two evaluation boards were designed, and total equivalent model was constructed by taking into account the parasitic inductances of traces on a board Then, frequency-domain analysis was executed to find anti-resonance peaks in impedance properties for the switching loop Next, time-domain simulation was executed by considering parasitic inductances Finally, the optimal condition to suppress the ringing noise and electromagnetic radiation was confirmed by adjusting the switching loop into the critical damping condition

High-speed data transmission system using half mode substrate integrated waveguide

Abstract: A high-speed data transmission system using half mode substrate integrated waveguide (HMSIW) is proposed in this paper The HMSIW transmits the signal by TE 05,0 mode so the channel bandwidth is from the cutoff frequency of TE 05,0 mode to the cutoff frequency of TE 15,0 mode In contrast, the traditional SIW transmits the signal by TE 10 mode and the channel bandwidth is from the cutoff frequency of TE 10 mode to the cutoff frequency of TE 20 mode Therefore, the bandwidth of the proposed HMSIW is 2 times larger than that of the traditional SIW with 2 times waveguide width of HMSIW Comparison between the interconnect systems based on HMSIW and SIW shows that the HMSIW-based interconnect system has a better performance in high-speed data transmission The data transmission rate of the proposed HMSIW system can reach up to 75 Gbps while that of the traditional SIW system is only 5Gbps with the same condition

Null field preconditioner for fast 3D full-wave MoM package-board extraction

Abstract: In this paper, a preconditioning technique based on the null field method is presented to accelerate the convergence of fast near-linear complexity iterative Method of Moments (MoM) solution For large-scale package-board 3D full-wave parasitic extraction, the solution time is often prohibitive for use in a design-cycle which might necessitate several analysis stages The bottleneck is often the slow-convergence of the Krylov subspace-based iterative solution Since the null field method scales the near field interactions to a block-diagonal form it can be used as an efficient preconditioner as shown in the numerical experiments

Fast and accurate technique to decompose jitter for very long pattern length waveform

Abstract: Protocols such as CEI, 10G Ethernet and PCIe Gen3 are requiring very long pattern length stress signals such as PRBS-23 and PRBS-31 to claim compliance and ensure robustness. Unfortunately, there is equipment limitation to directly measure very long pattern signals especially on oscilloscopes due to memory size and signal processing power. Thus, new jitter decomposition algorithms are introduced to measure these long stress patterns through behavioral modeling [1–3]. However, there are accuracy concerns with these new measurement methodologies because of incidences of false results when users attempt to qualify or debug a circuit. This paper will explore the limitations of different jitter decomposition algorithms from major equipment vendors in the industry when measuring very long pattern length waveforms. We will also provide the measurement method and calculations required to obtain the correct jitter decomposition. Correlation of the calculated number against direct measurement using bit error rate tester (BERT) is also done to prove the hypothesis and validate accuracy of the methodology. The findings in this paper are very beneficial in assisting the industry to perform accurate jitter measurements with shorter test time to achieve robust designs as well as prevent precious resources from being spent on investigating false failures. The findings also allow companies to show that their products are tested under stringent conditions that satisfy customer requirements.

Design and analysis of magnetically coupled coil structures for PCB-to-active interposer wireless power transfer in 2.5D/3D-IC

Abstract: In this study, magnetically coupled coil design for high efficiency wireless power transfer (WPT) in PCB-toactive silicon (Si) interposer is proposed and analyzed using Z-parameter analysis. For strong magnetic coupling between transmitter (Tx) coil on PCB and receiver (Rx) coil on Si-interposer, each coil structure is selected considering process dimension difference between PCB and Si-interposer. The equivalent circuit models for Tx coil on PCB and Rx coil on Si-interposer are suggested. Especially, the Rx coil model includes lossy Si-substrate characteristics and eddy current effect. In addition, analytical model for vertically aligned Tx coil and Rx coil in 2.5D/3D-IC is developed by considering LC resonance. All the proposed equivalent circuit models are analyzed by comparing Z-parameters (Z 11 ) with 3D EM simulation results. In this coil system, series-series WPT topology is applied to achieve high power transfer efficiency (PTE) and maintain a constant resonant frequency regardless of load impedance. The resonant frequency for high PTE is decided to be 100 MHz.

Vref optimization in DDR4 RDIMMs for improved timing margins

Abstract: JEDEC DDR4 SDRAM adopted the internal Data (DQ) reference voltage (VREFDQ) generation scheme as opposed to DDR3 SDRAM where VREF was generated by an external device that produced fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time With the introduction of Per DRAM Addressability (PDA) in DDR4 memory and the internal VREF combined, discussed in this paper is a novel approach to determine the best VREF settings for a given topology We will use memory controller built-in-self-test (MCBIST) to get a stressed pattern in place of simple Multi Purpose Register (MPR) data pattern and will be exercised as part of post DRAM training Data pattern complexity, total training time and accuracy of training are investigated and optimized Initial training of the DRAM is done with the initial VREF calculated based on driver strength and On Die Termination (ODT) condition Complexities of different VREF settings are applied on multiple ranks in the same DIMM using the PDA to maximize timing margin and power efficiency Per-DRAM VREF training has been also performed using PDA to study tradeoff between timing margin and total training time Our results show significant benefits with respect to PDA vs rank basis Vref training

Novel target impedance for power distribution network of simultaneous switching output (SSO) buffers

Abstract: The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.

Modular Power System and bus bar scheme in high power communication satellite

Abstract: This paper elaborates implementation of new and advanced concepts such as Modular Power System and bus bar scheme for power distribution in ISRO's high power communication satellite. The advantages of using Modular Power System vs. conventional power packages, details of new design and realization of Modular Power System are discussed. New mechanical housings realized for high power communication satellite are described. Usage of bus bar for power distribution has many advantages (as compared to wired harness) such as, reduced power distribution loss, higher current carrying capability, improved EMC performance, better thermal management and scope for mass reduction.

Effect of layered media on the parallel plate impedance of printed circuit boards

Abstract: This paper evaluates the impact of layered media on the parallel plate impedance of printed circuit boards. In the parallel plate impedance computation using the radial waveguide method (RWM) for infinite planes and a contour integral method (CIM) for finite planes, the layered nature of investigated structures can be accounted for by effective wave numbers. Here, the effective wave numbers are obtained using either an exact solution from the transverse resonance method (TRM) or adopting approximations based on the assumption of quasi-TEM fields and the applicability of suitable averages. The wave numbers obtained with these techniques are compared for typical structures of interest, and the parallel plate impedance computed with effective wave numbers is evaluated and compared to a full wave solution. The results show that a comparatively simple approximation for the effective wave number is sufficient for an accurate parallel plate impedance calculation.

De-embedding method and segmentation approach using full wave solver for high speed channels in PCB/package co-design

Abstract: This paper proposes an accurate and effective modeling approach by incorporating a de-embedding method when de-composing electrically large PCB/Package models into smaller sub-models. The proposed technique allows to accurately taking into account the discontinuities at the PCB/package interface while reducing the simulation effort.

Fast incremental 3D full-wave analysis for package-board design iterations via eigen-GCR

Abstract: In a typical design cycle many iterations on the package-board-system layout may be performed to meet design specifications. In the process, the analysis step needs to be repeated as many times as the number of layout variants. The cost of analysis, especially if using a 3D fullwave extraction methodology, therefore becomes prohibitive for large-scale analysis in the design process. In this paper, a methodology is proposed to expedite analysis of subsequent layout iterations based on information stored from previous layout solution. The efficiency of a Method of Moments (MoM) based 3D full-wave solution is limited by the slow convergence of the iterative solver in a fast solver framework. In this work, eigen-vectors from a previously solved layout is used to augment to the Krylov subspace to expedite the convergence of a Generalized Conjugate Residual (GCR)-based iterative solution for next layout. Numerical results demonstrate up to 40% improvement in the convergence properties using the proposed GCR method.

High-speed data transmission system based on QPSK scheme in substrate integrated waveguide

Abstract: Substrate integrated waveguide (SIW) is regarded as an available interconnects solution for high-speed data transmission. In this paper, in order to further improve the data rate and bandwidth usage, an SIW interconnect system based on Quadrature Phase Shift Keying (QPSK) modulation and demodulation technique is proposed. The associated theoretical models validate the feasibility of the presented system. A fabricated SIW prototype with 14–28 GHz bandwidth is experimentally evaluated in the developed SIW QPSK data communication system. Experimental results demonstrate that an excellent eye opening and low error rates are obtained with different Pseudo Random Binary Sequence (PRBS) bit sequences at the rate of 10 Gb/s. Compared with traditional mixing modulation scheme, our proposed system can improve transmission rate from 5 Gb/s to 10 Gb/s and achieve error-free operation (BER<10−12) with 27−1 pattern.

Design space exploration of Through Silicon Vias for high-speed, low loss vertical links

Abstract: In this paper, performance analysis of Through Silicon Vias (TSVs) considering various bonding techniques is investigated In that, bonding of TSVs using Cu-Sn microbumps, Cu-Ag microbumps and Cu-Cu direct bonding is considered We present SPICE-compatible equivalent circuits for these configurations using exhaustive simulations performed on electromagnetic field solver, Ansys Q3D We analyze these TSV configurations for various interconnect performance metrics, such as delay, energy delay product, energy per bit, insertion loss and bandwidth density Our analysis gives physical insights into the effect of microbumps/discontinuities on the TSV performance Our analytical results show that vertical interconnects using Cu-Cu direct bonding significantly outperforms those using Cu-Ag or Cu-Sn microbumps, which makes it an excellent candidate for high-speed, low loss vertical links

Indirect contact probing method for characterizing via arrays in electronic packaging

Abstract: In this paper, an indirect contact probing method for via arrays is proposed. The proposed method characterizes via arrays without contact damage from probe tips, and it does not require additional control and sensor electronics. To execute the indirect contact method, firstly, multiple measurements on specially designed calibration vias are performed to obtain the dielectric contactor characteristic. The characterized contactor layer is de-embedded when the actual via arrays as the device-under-tests (DUTs) are extracted. In simulations at frequencies ranging from 800 MHz to 25 GHz, it is confirmed that defects on via arrays can be successfully identified from the indirect-contact probing.

Eye-height/width prediction from S-Parameters using bounded size training set for ANN

Abstract: Validation of high-speed interface performance in a given design space from a Signal Integrity (SI) perspective requires Bit Error Rate (BER) computation Eye Height (EH) and Eye Width (EW) are used to determine the quality of an interface for a given set of design parameters and frequency of operation EH, EW and BER estimation requires Time Domain (TD) simulation of complex channel models over billions of bits, which is a time, compute power and memory intensive process Statistical and optimization techniques such as Design of Experiments (DoE) based on generation of design sets that span the design space optimally exist today However, it has been shown that DoE based simulations might result in in-accurate sensitivity analysis for highly nonlinear design spaces Also, the size of a DoE set scales exponentially with the number of design variables It has been shown in [5] that TD metrics EH and EW, in absence of cross-talk, can be mapped from FD metrics like Return Loss (RL) and Insertion Loss (IL) using Artificial Neural Networks (ANN) The training of the ANNs requires DoE for the existing method In this paper, an alternative technique to DoE, for generating a training set for ANN is presented, which remains constant over several number of design variables, and scales only in the number of FD metrics used to map to TD metrics and the number of samples in FD Simulations for SATA 30 channel topology with and without cross-talk in TD are presented to quantify the accuracy of the said approach

Hybrid silicon and glass interposer for combined optical and memory system-in-package

Abstract: This paper proposes a low-cost packaging configuration for a combined optical and memory system-in-package. The proposed hybrid silicon and glass configuration meets the wiring density required for HBM and high-frequency characteristics required for optical IC wiring. We also built and tested a wiring TEG to evaluate the high-frequency performance of 25 Gbps differential transmission wiring for optical ICs in the glass interposer region, thereby seeking to minimize losses and reduce power consumption. Experiments showed satisfactory transfer characteristics of □0.8 dB/cm.

EMI coupling to command lines due to solar array switching strings in spacecraft

Abstract: The satellite as a system consists of various bundles of harness interconnections between subsystems, across the panels. These bundles of harness consist of different types of cables - power lines, data lines, command lines. Power lines from solar array also carry switching currents from the solar array switching circuits. When all these cables are bundled together, it essentially brings out the problem of unintentional electromagnetic energy coupling between the wires. This paper analyzes the amount of coupling in a typical command line placed in close proximity to the power lines carrying switching currents. It is reported that few in-orbit spacecraft on-board anomalies are attributed to spurious commanding due to cable coupling between the command lines and the switching power lines. This analysis considers the different harness configurations of the power lines where such possibilities exist.

Validating 2.5D System-in-Package inter-die communication on silicon interposer

Abstract: 2.5D Integrated Circuit (IC) technology is a new approach in designing System-in-Package (SiP) which offer flexibility in mixing dice available in different technology nodes and applications inside a single package and interconnecting them on silicon interposer. This results in reducing overall system complexity, less on-board components, cost and size. This technology is capable of powering next generation ICs targeted towards tablets, cell phones and portable electronics. 2.5D technology differs from existing 2D-IC technologies such as System-on-Chip (SoC), Multi-Chip Module (MCM) and System-in-Package (SiP) in terms of usage of silicon interposer as a medium for inter-die communication. This provides high bandwidth, low power dissipation and overcomes routing congestion. Sample use cases of 2.5D are explained in the paper. A test chip project showcases functional working of 2.5D IC on Printed Circuit Board (PCB). Finally, usage of 2.5D-IC technology for multi-domain, multi-manufacturing node is been proposed and concluded.

Study on power supply noise and electromagnetic radiation in relation to chip-package anti-resonance

Abstract: Electromagnetic radiation is strongly related to power integrity of digital electronic systems In order to estimate power supply noise exactly, chip-package-board co-design becomes more important to estimate the properties of chip-package anti-resonance In particular, power supply noise is very sensitive to Q factor value of the anti-resonance In this paper, three test chips were designed with different on-chip PDN properties These three chips were intended to have typical characteristics; oscillatory region and critical damped conditions By using these chips, the relationships between power supply noises and Q factor values of chip-package anti-resonances were extensively studied by using QFP and BGA packages Furthermore, both electromagnetic near-field and far-field radiation were evaluated It has been proved that electromagnetic radiation was dramatically reduced by establishing the critical damping condition in chip-package-board co-design

A novel common-mode filter (CMF) design based on signal interference technique

Abstract: The signal interference technique is firstly employed to design the common-mode filter (CMF) for differential digital circuit applications. Using the network analysis, design curves for three common-mode transmission zeros are available by simple steps. A test sample is realized in two-layer PCB. The fractional bandwidth of common-mode suppression band (|S cc21 | dd21 |) is better than −3 dB from DC up to 10 GHz in measurement. The flat differential-mode group delay implies this CMF can preserve good signal integrity, which is obvious by eye diagram measurement in time domain.

Challenges of using flex cables in high speed serial links

Abstract: Blade servers are constantly moving towards higher data rates and smaller form factor resulting in complex routing choices to accommodate various chassis configurations. Flexible printed circuit (FPC) cables or flex cables serve as a good choice for interconnect medium in such densely configured server systems. In this paper, various challenges involved in designing a high speed serial link using flex cables are discussed. The impact of flex cable stack-up choice on signal integrity (SI) performance (impedance and loss) is studied. Sensitivity analysis on flex cable impedance and loss are performed by taking various flex cable design parameters into account using 3-D full wave modeling results. Best design practices needed for FPC cables are discussed in detail. Finally, SATA 3.0 interface is used as an example to demonstrate the design trade-offs of flex cable.

Efficient computation of capacitive coupling between planar and cylindrical interconnections

Abstract: For the efficiency improvement of 3D path-finding methodology, this paper presents the reduction of computational cost in the calculation of capacitive coupling between planar and cylindrical structures. The previously used global adaptive quadrature for integrations involving the angular variable is replaced by a simple trapezoidal quadrature with the double-exponential transformation. Also, the other integrations over planar variables is approximated to a simple summation. From the verifications of the proposed technique for various coupling structures shows that the updated modeling method reduces the computation time by up to 12%.

A case study of BGA package for high speed channel with non-ideal ground induced resonance conditions

Abstract: Proper transmission of high speed signal requires sufficiently high bandwidth of the medium. The reference planes play a vital role in achieving distortion-free signal propagation. In this paper a BGA package design exhibiting resonance conditions in insertion loss is analyzed. Analysis led to ground path issues caused by return current density congestions. Improvement in ground return path layout led to elimination of resonance conditions. Re-designed package is meeting the intended design target for HDMI 2.0 standards.

Inter layer crosstalk between stripline and metal patch

Abstract: The crosstalk between stripline and the power plane on an adjacent layer in a multilayer printed circuit board (PCB) are analyzed and shown Different methods of suppressing this crosstalk effect are discussed and compared

Crosstalk reduction for compact optical transceiver module

Abstract: We propose crosstalk reduction for the compact optical transceiver module Crosstalk is composed of three elements: crosstalk resulting from electromagnetic coupling between adjacent signal lines, crosstalk resulting from electromagnetic coupling between transmission and reception, and crosstalk resulting from source impedance Each element was reduced by adding a shield pattern and reducing the impedance of the pattern and that of the source pattern We fabricated a module and demonstrated error-free transmission with simultaneous operation at 25 Gb/s by using a 231−1 pseudo random bit stream (PRBS)

Methodology to design SATA 3.0 channels with re-driver

Abstract: As signal speeds continue to increase, maintaining signal quality has become a greater challenge for signal integrity (SI) engineers Migrating a system to a next-generation interface technology operating at higher speeds brings with it increased sensitivity to attenuation and jitter that can severely curtail reach and reliability In order to meet the interface specification, expensive choices such as low loss material and expensive connectors are needed Addition of re-drivers to a channel is becoming a popular and relatively in-expensive solution to enhance SI performance The selection of re-drivers presents some of design and simulation challenges over high speed channels This paper describes a methodology which enables SI engineers to effectively simulate a SATA 30 channel with re-drivers The proposed methodology is further implemented in one of the server systems to evaluate the data correctness for re-driver usage in the high speed SATA channel Simulation and measurement data are correlated to validate the effectiveness of re-driver simulation A Design of Experiment (DoE) is created to address the simulation challenges and accuracy of the simulation result DoE also addresses the statistical analysis to understand the re-driver parameters that impact eye diagram and jitter Design engineers can use the flow and methodology introduced in this paper to evaluate channel performance for High Volume Manufacturing (HVM) for their proposed topology

Resonant power supply noise reduction using on-die decoupling capacitors embedded in organic interposer

Abstract: This paper demonstrates an on-die STO thin film decoupling capacitor used for resonant power supply noise reduction The on-die STO capacitor consists of STO whose dielectric constant is about 20 and is sandwitched by Cu films in an organic interposer on which we can also draw connection wires by Cu deposition The capacitor was attached directly on our test chip using ball banding technique through PADs connection Our experimental results using a real silicon chip shows that our on-die STO capacitor achieved significant resonant supply noise reduction This result also shows that we can reduce the power supply noise without chip area penalty, and also it enables us to modify the noise characteristics even after the chip fabrication process

Impact of sockets in Package-On-Package electrical validation & design considerations

Abstract: For next generation mobile tablet platforms, cost and form factor, power and performance are the key vectors which lead to design wins SoCs(System-On-Chip) are fast becoming the solution for these platforms which contain most of the interfaces in a single package To reduce power and real estate the trend is to design denser SoC packages which has further led to many PoP (Package-On-Package) designs These PoP designs are gaining momentum, which give premium tablets with low power, reduced real estate, higher speed and better performance But these designs come with its own challenges especially on the system and electrical validation side For example any debugging of system memory interface needs access to memory signals which is all concealed in a PoP now This led to the use of different kind of sockets and validation cards, which can give access to needed signals Sockets are again important for volume characterization of SoC or memory parts as well This raises few interesting questions:- at higher speeds are sockets reliable? Do sockets alter the electrical behavior of a particular interface? If yes, how much it will alter? Do we have different variables to tune the socket behavior? Can we predict the socket impact and manipulate the data? In this paper we try to answer these important questions with simulation and lab data, based on an Intel platform with special emphasis on system memory interface