Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2015"

Design optimization of high bandwidth memory (HBM) interposer considering signal integrity

Abstract: As total system bandwidth increased, memory industry has been imposed to satisfy its requirements. At last, innovative next generation memory named high bandwidth memory (HBM) with extremely fine micro-bump pitch of its bottom die is introduced for terabytes/s bandwidth graphics module. To establish HBM based graphics module, it becomes essential to fabricate silicon interposer due to its capability to process narrow signal width and space. Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. To design HBM interposer successfully, the signal optimization of HBM interposer channels must be preceded thoroughly. In this paper, design optimization of top metal signals of HBM interposer considering routing feasibility is proposed. In order to analyze channel performance to determine optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM interposer are analyzed by comparing eye-opening voltage and timing jitter with 3D electromagnetic (EM) simulation results. Based on this proposed optimization design, not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.

Power distribution network design and optimization based on frequency dependent target impedance

Abstract: In this paper, frequency dependent target impedance is proposed for optimal Power Distribution Network (PDN) design Target impedance indicates how much and where decoupling capacitors should be located in the PDNs therefore it directly affects performance of the electrical systems or manufacturing cost In this paper, frequency dependent target impedance considering IC's power current spectrum is proposed Based on the proposed target impedance, GPU's VDD PDN is designed so that the hierarchical PDN impedance is maintained bellow the proposed target impedance in frequency domain We simulated designed PDN with GPU chip's signal model in the time domain to verify the proposed target impedance Simultaneous Switching Noise (SSN) in the GPU chip PDN was suppressed bellow the target which is 5% of the supply voltage based on proposed design Compared to the conventional target impedance, proposed target impedance allowed more flexible design and at the same time satisfied the design criterion

Measurement and analysis of the electromagnetic emanations from video display interface

Abstract: The monitor display can be eavesdropped by measuring and analyzing the compromising electromagnetic emanations. These electromagnetic emanations of video display interfaces are generated by electric signals on the display panel or the cable between the computer and the monitor. In this paper, the radiated signals from video display interface of Video Graphics Array (VGA) cable are measured and analyzed. The leaked signals are received by near-field probe connected to the digital oscilloscope. The received signals are reconstructed by signal processing, and reconstructed display is compared with original display.

Analysis of external force dependent lumped RLGC model of high-bandwidth and high-density silicone rubber socket

Abstract: In this paper, structural and electrical characteristic deviations of silicone rubber sockets are analyzed depending on external force based on its lumped RLGC model. Electrical performances heavily depend on compression rate of the silicone rubber socket. Thus, study on the structural and electrical characteristic deviations of the silicone rubber socket depending on external force is needed for reliable tests. The deviations are analyzed based on an assumption based simplified equivalent model of the silicone rubber socket. For verification, a 3D electromagnetic (EM) simulation program is used and its results are compared with that of proposed RLGC models in the frequency domain. The electrical performance of the RLGC model is nearly identical to that of 3D EM simulation result. In addition, the electrical performance of the compressed silicone rubber socket is also nearly identical to that of a solder ball when it is compressed at different compression ratio.

Electrical characteristics analysis and comparison between through silicon via(TSV) and through glass via(TGV)

Abstract: The electrical characteristics of silicon and glass interposer channel are heavily affected by the design of through silicon via (TSV) and through glass via (TGV). In this paper, we analyzed the overall signal integrity of glass and silicon interposer channel including through package via. To compare electrical property between silicon and glass, we simulated these channels in frequency-domain and time-domain. We observed s-parameter of single and multiple via transition channel. Moreover we compared the characteristic impedance and eye diagram simulation results. Finally, we observed the change of electrical characteristics when the impedance mismatch is occurred at via pad.

Electrical approach to acoustic noise for MLCCs of power delivery network in mobile system

Abstract: In this paper, the authors propose an effective methodology to detect capacitors generating audible acoustic noise in power delivery network of mobile system. Most of capacitors are exposed to coupling noises; TDMA (Time Division Multiple Access) in GSM (Global System for Mobile communication) operates in every 217Hz. The dielectric material and electrolyte of MLCCs (Multilayer Ceramic Capacitors) have stressed due to AC voltage droop synchronous to TDMA operation. Hence, the voltage droop on MLCCs can be used as an electrical key element to figure out how much MLCCs are vibrating among hundreds of capacitors in mobile system. AC voltage droop on MLCCs is examined by measurement and simulation as well as are well correlated. In addition to, an amplitude of each MLCC is measured in its TDMA harmonics and the most vibrated MLCC is consistent with the MLCC which is the most dropped in every 217Hz.

Design space exploration of nanoscale interconnects with rough surfaces

Abstract: This paper investigates the effect of surface roughness on interconnect parasitics (RLC per unit length) and performance metrics, such as delay, energy-delay product, bandwidth density, insertion loss and attenuation coefficient of nanoscale on-chip interconnects using 3D EM solver. Our analysis focuses on two industry relevant technology nodes i.e. 13.7 nm and 22 nm. We observe that there is a severe penalty on the performance of interconnects due to surface roughness when analyzed over broadband frequencies. Mandelbrot-Weierstrass (MW) function is used here to define the rough surface profile and the data points obtained from the plot of M-W function are directly used in HFSS for the development of rough conductor interconnect structure. We also present the computational overhead incurred during simulation of rough interconnects.

Fast transient electro-thermal simulation of on-chip interconnects in the presence of ESD pulses

Abstract: An efficient transient electro-thermal simulation of on-chip interconnects under electrostatic discharge (ESD) stress is carried out with the alternating-direction-implicit (ADI) method. Both temperature-dependence of electrical resistivity and Joule heating effect are taking into account in the modeling. With the ADI technique, the heat conduction equations in the matrix form are derived at three sub-time steps, which can be calculated with linear computational complexity and memory requirement. The accuracy and high-efficiency of the proposed method are demonstrated by the numerical examples.

Analytical calculation of electromagnetic fields near parallel power planes with decoupling capacitors for RF interference estimation

Abstract: An analytical method to calculate the electric- and magnetic fields near a planar PDN with decoupling capacitors has been proposed. Magnetic current source along the plane edges with multiple decoupling capacitors is calculated using the cavity resonant model. The electric- and magnetic fields in the near field region calculated from the magnetic currents are validated with the results obtained using PEEC method.

Fast calculation of system-level ESD noise coupling to a microstrip line using PEEC method

Abstract: The system-level ESD coupling on a microstrip line is calculated using the partial element equivalent circuit (PEEC) method both in frequency and time domains A simplified MNA matrix for the victim trace is proposed to quickly calculate the charge and current induced due to the ESD event The calculated coupling transfer impedance and the ESD waveforms coupled on the traces are validated by comparison with measurements both in frequency and time domains

Crosstalk analysis and suppression for differential TSVs in 3-D integration

Abstract: Differential through silicon vias (TSVs) are commonly used for the differential signaling in three-dimensional (3-D) integration, which may be disturbed by the electromagnetic field of the neighboring signal/ground paths. In this paper, the equivalent circuit model of the differential TSVs is established. Then the induced noise on the differential TSVs from the neighboring single-ended and differential TSVs are evaluated, in terms of the interference distance and the coupling strength inside the differential TSVs. To mitigate the noise interference, a twisted differential TSVs structure and an offset twisted differential TSVs arrangement are proposed. Results show that the noise magnitude can be effectively reduced by the proposed structures in the frequency domain and time domain.

Analysis of illuminated bent microstrip line based on Baum-Liu-Tesche (BLT) equation

Abstract: This paper presents an effective method based on the Baum-Liu-Tesche (BLT) equation for the simulation of microstrip lines with discontinuities in the presence of electromagnetic illuminations. A right-angled bend is taken into account in the modeling and simulation, as a typical discontinuity of microstrip line. With the BLT equation and superposition principle, the terminal voltages of microstrip lines can be obtained. First, the case of plane wave incidence is analyzed. The validity and accuracy of the proposed method are illustrated by the numerical results. Then, the microstrip bend is illuminated by the near field of a dielectric resonator antenna. The relative error of voltage amplitudes is within 8%, when compared with the full-wave simulated results with ANSYS HFSS.

Electric and magnetic field shielding evaluation of board level shield can using TEM cell

Abstract: This paper proposes a simple electric and magnetic field shielding evaluation method of board level shield can using Transverse Electro-Magnetic cell (TEM cell). Small sized electric and magnetic probes (antennas) are installed on the top of a TEM cell with and without shield can below the probe, and 3-port S-parameters are measured, which are used to calculate the electric and magnetic dipole moments of the probes transferred to the other two ports in the TEM cell. The calculated data effectively evaluated the shielding effectiveness of the shield cans with various ventilation holes in both electric field and magnetic field, separately. Finally, the measured shielding effectiveness was validated by numerical simulation and thus reliable results were obtained.

Non-orthogonal 2.5D PEEC for power integrity analysis

Abstract: Power distribution network (PDN) of a multilayered PCB is designed to supply low noise and stable power to ICs. Reduced voltage levels, increased current requirements make it challenging to attain the desired PDN impedance profile. It is therefore necessary to have multiple design iterations for optimal performance of the PDN. 3D full-wave electromagnetic solvers like the Partial Element Equivalent Circuit (PEEC) method are time constrained and therefore ill-suited for early stage design. On the other hand, 2.5D tools have lower time and memory requirements and are reasonably accurate for planar power-ground structures. For example, Multilayered Finite Difference Method (MFDM) is a 2.5D formulation suitable for PDN analysis. However, present MFDM techniques are based on orthogonal meshes, such that power-ground planes with irregular shapes and holes require unnecessarily fine mesh at the boundary for a suitable staircase approximation. In this paper, a non-orthogonal 2.5D PEEC formulation is proposed to alleviate this problem. Numerical results using quadrilateral meshes demonstrate good accuracy as compared to 3D full-wave formulation for planar geometries.

Analytical calculation of pattern-dependent simultaneous switching outputs (SSO) due to power supply fluctuations

Abstract: An equivalent circuit model for simultaneous switching output (SSO) drivers is constructed. The simultaneous differential equations for the pattern-dependent SSO waveforms are built from the model and analytically solved. The analytical solutions are validated by comparison with the HSPICE simulation results. The effects of the number of pull-up and pull-down transitions are also investigated from the case studies.

Statistical estimation of characteristic impedance distribution caused by PCB manufacturing process variation in high-speed mobile channels

Abstract: In recent mobile systems, the fraction defective of the PCB channels increases with the increase of the PCB manufacturing process variation, when the other conditions affecting the PCB manufacturing are the same as before. From the experimental verification, we confirm that the distribution of the characteristic impedance is critically increased by the process variation. To reduce the fraction defective, we need to estimate the distribution of the characteristic impedance in the pre-design step as the criterion representing the deleterious effect of the process variation on the PCB channels. In this paper, we propose the statistical estimation method estimating the distribution of the characteristic impedance. Additionally, we define the noteworthy range of the characteristic impedance as the quantitative indicator representing the distribution of the characteristic impedance for the practical use.

Virtual metrology for TSV etch depth measurement using optical emission spectroscopy

Abstract: In TSV fabrication process, TSV depth measurement of all wafers is essential to maintain high yield and wafer quality. However, there are limits such as high cost and (low throughput using an actual metrology, i.e. scanning electron microscope (SEM), and only few wafers in a lot are monitored in practice. In this research, we presented a virtual metrology (VM) system for TSV depth measurement after etching process. The proposed VM system is based on PLS regression (PLSR) and neural networks (NN) using OES data to predict TSV depth. Real operational data taken during TSVs etching process along with 80 and 25 μm diameter TSVs are used in order to verify the quality of the prediction accuracy of the proposed VM model.

Acceleration of large electromagnetic simulation including non-orthogonally aligned thin structures by using multi-GPU HIE/C-FDTD method

Abstract: In this paper, multi-graphics processing units (GPU) hybrid implicit-explicit/conformal finite-difference time-domain (HIE/C-FDTD) method is proposed for the large efficient electromagnetic simulations. The HIE/C-FDTD method is constructed by combination of the HIE-FDTD method and the C-FDTD method. The HIE/C-FDTD method can adopt a larger time step size than that for the conventional FDTD method and can use the large cells. In addition, the HIE/C-FDTD method is suitable for parallel computing such as GPU Computing. First, the HIE/C-FDTD method is reviewed briefly. Next, the proposed method is described. Finally, the efficiency of the proposed method is verified by some numerical results.

Efficient calculation of EMI factors from power distribution network using cavity resonance circuit model

Abstract: The radiated emissions from the planar power distribution network (PDN) with decoupling capacitors are efficiently calculated using the cavity resonance circuit model. The emission from the polarization currents in dielectric medium is included in the calculation. The proposed calculation method is validated with the numerical computation results using the partial element equivalent circuit (PEEC) method. The radiated emission due to each current component is analyzed using the proposed method. Also, the effects of PDN geometry on the radiated emission are investigated with several case studies.

Quantifying the impact of differential-to-common mode conversion on RFI

Abstract: Although differential signaling has low electromagnetic emission levels, unwanted differential-to-common mode conversion poses a significant concern in radio-frequency interference issues. However, its compliance limit is specified without justification in most high-speed serial interfaces. This paper employs a quantitative approach to suggest a reasonable target.

Analysis of through glass via (TGV) noise coupling effect to noise figure of 2.4GHz LNA on glass interposer

Abstract: Through glass via(TGV)-TGV coupling noise could badly affect to glass interposer based 2.5D/3D ICs RF system. RF system specification is specified with RF sensitivity. And RF sensitivity is dominantly determined by LNA noise figure. Normally LNA noise figure is calculated with only device and thermal noise since it assumes no noise coupling is exist. For estimating LNA noise figure degradation by TGV-TGV coupling noise, we proposed modified LNA noise figure equation which includes coupling noise effect. For analysis, we designed 2.4GHz LNA schematic and proposed TGV-TGV coupling structure which includes TGVs and channel lines. And then we analyzed output waveform of the LNA with TGV-TGV noise coupling on time domain and frequency domain when single tone noise is injected to LNA components. Finally we estimated noise figure degradation by single tone switching noise.

Design of an on-interposer passive equalizer embedded on a ground plane for 30Gbps serial data transmission

Abstract: In this paper, a new on-interposer passive equalizer was proposed for chip-to-chip high-speed serial data transmission. It is a coil-shaped shunt metal line and embedded on a ground plane to maximize channel routability. Since the proposed equalizer is based on the fine pitch design rules of silicon interposer, it can be integrated in a small area. Equalizing method is based on a high pass filter composed of an inductance and a resistance of the proposed structure. It achieves wide-band equalization up to data rate of 30 Gbps. Performance of the proposed equalizer is verified using frequency- and time-domain simulation. By applying the proposed equalizer to 30 Gbps channel, eye-height was improved by 13.4 % of input voltage and timing jitter was reduced by 5.5 % of one unit interval.

LTCC package for high-bandwidth logic to memory interconnection

Abstract: Advancements in packaging technologies are required to meet the future bandwidth, and space- and energy- efficient demands of ICT systems. One of the key technologies is 2.5D packaging using a silicon interposer with through silicon vias (TSVs). However, forming the TSV and thinning the wafer makes the Si interposer's cost high. Furthermore, using an organic substrate causes high electrical losses and warpage. We propose a low-temperature co-fired ceramics (LTCC) package with fine line layers to help alleviate these problems. The surface of the LTCC substrate is made very flat, so fine patterns with line/space that is 2/2μm can be formed. The LTCC package has been expected to decrease the necessary costs by simplifying the assembly process and introducing a panel-based process. Moreover, the LTCC substrate is more reliable than a Si interposer with an organic substrate and can transmit a high data rate signal at a lower loss. We demonstrated the possibility of high Bandwidth Memory (HBM) routing using the LTCC package.

Design of active connector for high speed serial link interconnection

Abstract: In this paper, an active connector is designed and simulated for high speed serial link interconnection. The connector design consists of three main parts; plug, receptacle, and paddle board. For achieving high bandwidth performance, the key difference of the proposed connector, comparison to the general connector structure, is that the active equalizer is integrated on the paddle board. The connector model is designed and simulated for this study, and the result shows this proposed connector structure is good for high bandwidth interconnection up to 20 Gbps.

Power integrity co-analysis and design in a PCB with BGA package using transmission matrix method

Abstract: Power integrity (PI) is among the main concerns in the design process of multilayer packages and printed circuit boards (PCBs) Based on Transmission Matrix Method (TMM), the PI performance of a Ball grid array (BGA) package mounted on a PCB is investigated in this paper The power/ground planes and the power/ground balls on a PCB and package are entirely equivalent to distributed RLGC circuits model and co-analyzed From this model, power performance could be computed with high efficiency Moreover, a design rule of power/ground balls arrangement is obtained by reducing the equivalent inductance and equivalent capacitance of BGA for good power integrity performance

A case study: Power measurement and optimization of DDR3 DIMM in servers

Abstract: Optimization of memory power is an important design objective in any computer device. However, servers are especially a challenge because the number of DRAMs are large and in aggregate can consume up to 40% of the overall system power. This paper presents power measurement experiments under a variety of server system conditions. Some techniques are proposed to optimize the overall power consumption. The experiments must be carefully planned with defined workloads and voltage regulators of sufficient resolution so that the measurements can be used for both analysis and prediction. The primary objective of this work is to accurately project the power demand from the hardware measurements to confirm that all system DRAM configurations stay within their power budget.

Surface current distribution for PCB PDNGeometry

Abstract: Surface current distribution provides an intuitive perspective on how the current flows, which is critical for high speed design. The surface current distribution for the power distribution network (PDN) in printed circuit board (PCB) is related to the input impedance observed by the IC looking into the PCB PDN. Two different principle methods are used to describe the current distribution, namely plane-pair PEEC (PPP) and resonant cavity model.

A fast statistical eye-diagram estimation method including internal PDN noise of pseudo-differential receiver buffer

Abstract: In this paper, a fast statistical eye-diagram estimation method including internal PDN noise of pseudo-differential receiver buffer is proposed. For fast BER calculation, the optimal-sized sets of receiver input and internal PDN noise for one unit-interval are employed. They are extracted based on the double-edge responses of the channel and the multiple-edge responses of the pseudo-differential receiver buffer at power/ground nets, respectively. Fast estimation time and accuracy of the proposed method are successfully verified by comparing to the SPICE-based transient simulation results.

Analysis of high frequency characteristics of power inverter using accurate IGBT model based on datasheet and measurement

Abstract: The output voltage and current from dc-ac inverter generate switching noises and may cause electromagnetic interference (EMI) problems to other electronic systems. To analyze high frequency switching behavior of an inverter accurately, an accurate IGBT model is essential. In this study, an insulated gate bipolar transistor (IGBT) is modeled using datasheet and measurement data to analyze the high frequency characteristics of a high-power full-bridge inverter. The effectiveness of the proposed IGBT model is verified by comparing the simulated results of the inverter using the proposed IGBT model with measured results in frequency domain.

A high-performance vertical substrate noise isolation method for 3D ICs

Abstract: In this paper, we have developed a new structure to suppress 3D noise coupling in 3D silicon substrates. This technique consists of contact arrays and grid ground planes. The contact arrays suppress the low-frequency noise while the grid ground suppresses the high-frequency noise. This isolation method can be used for noise suppression between circuits and/or TSVs, and it can be applied in 3D ICs with multiple dies. This method is more efficient compared to guard rings. Results show that it has significant and stable performance.