Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2018"

Heterogeneous SoC Integration with EMIB

Abstract: The challenges of yielding larger Silicon dies increases as the technology node shrinks. IP availability on the same technology node on the same industry process is also not always possible because of design complexity, features and schedule. This necessitates integration of smaller manageable dies from different processes and fabs to create SiPs. Integration of chiplets on the package is the trend to sustain performance across multiple generations of chip design. This work highlights the role of EMIB (Embedded Multi-Tile Interconnect Bridge) for heterogeneous silicon integration.

Machine Learning for Fast Characterization of Magnetic Logic Devices

Abstract: Non-charge-based logic devices are promising candidates for future logic circuits. Interest in studying and developing these devices has grown dramatically in the past decade as they possess key advantages over conventional CMOS technology. Due to their novel designs, a large number of micromagnetic simulations are required to fully characterize the behavior of these devices. The number and complexity of these simulations place large computational requirements on device development. We use state-of-the-art machine learning techniques to expedite identification of their behavior. Several intelligent sampling strategies are combined with machine learning multi-class classification models. These techniques are applied to a recently developed exchange-driven magnetic logic scheme that utilizes direct exchange coupling as the main driver.

Preliminary Application of Deep Learning to Design Space Exploration

Abstract: The increasing trend towards higher performance electronic systems has led to various challenges in design space exploration. Often times, interconnects in such systems are analyzed using CPU intensive fullwave EM simulations, making parameter sweeps in a very large design space impractical. In this paper, we propose using Deep Neural Networks (DNN) as a solution to cover the large design space using their generalization capability, i.e., predicting outside the range of training data. We show the performance of the proposed method on predicting the frequency dependent RLGC matrices of a multi-conductor microstrip transmission line.

Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects

Abstract: Graphene has become as one of the prospective on-chip VLSI interconnect materials due to its several superior electrical and mechanical properties. Graphene derived multi-layer graphene nanoribbon (MLGNR) has been investigated as one of the aptly suited on-chip VLSI interconnects. Long on-chip MLGNR interconnects are prone to various non-ideal effects such as signal degradation and crosstalk. The performance of the system deteriorates significantly as the length of interconnect increases. To mitigate this graving issue, novel buffer insertion technique for on-chip long MLGNR interconnects has been systematically presented and analyzed in the current paper. The practical CMOS driver-MLGNR interconnect-load model has been considered for analysis. The different analyses have been performed at 22nm technology node.

Crosstalk and EMI Reduction using enhanced Guard Trace Technique

Abstract: Client system design space is becoming aggressive every year and all these aggressive designs have more signal traces routed in any given area; whether in microstrip or in strip line. This is true for system mother board level as well as package substrate level. Guarding high speed signals by a co-planar grounded trace is the traditional way of reducing the crosstalk and EMI. This grounded trace will usually run along with the high-speed signal throughout the channel. But as the speeds are going higher, most of the interface margins are still limited by crosstalk and the proposed “Elevated guard trace technique” can further reduce crosstalk and EMI in order to increase overall system performance. This innovative technique of Guard trace can be utilized in microstrip layers routed with high speed signals to minimize EMI emissions significantly.

PDN design and sensitivity analysis using synthesized models in DDR SI/PI co-simulations

Abstract: A common method for analyzing a PCB Power Distribution Network (PDN) involves performing model extractions on a CAD layout, checking the impedance vs frequency plot, and using the model in transient simulations. The proposed method uses a synthesized RLC model as a replacement for CAD layout and that it closely mimics a realistic CAD layout extracted model. Such a synthesized model is easily created using self and transfer impedance equations (that can either be created manually or be incorporated into an algorithm for automatic generation). The RLC synthesized models are passive and causal and have been shown to eliminate common problems in transient simulations. The models can be created quickly and easily with varying PDN impedances and effective topologies and have been shown to correlate very well with models extracted from CAD layouts in both the frequency and time domains. Such models can potentially replace extracted PCB models and enable efficient design space exploration to determine PCB PDN targets. The technique can also be applied to PKG PDN models.

Transient and Crosstalk Analysis of Doped and Dielectric Inserted MLGNR Interconnects

Abstract: In the present work, performance of normal multilayer graphene nanoribbon (NMLGNR), doped MLGNR (DMLGNR) and dielectric inserted MLGNR (DiMLGNR) are analysed using coupled line interconnect system. The transient and crosstalk analysis of NMLGNR, DMLGNR and DiMLGNR interconnects are presented. By performing transient analysis, the average propagation delay for DiMLGNR exhibits the best performance amongst the three types of interconnect-systems under consideration. The crosstalk delay of DiMLGNR interconnect is 62.7% and 25.7% lesser compared to that of NMLGNR and DMLGNR interconnects respectively.

Impact of Via Stub Position on High Speed Serial Links

Abstract: While designing any interface, the impact of channel components like vias, trace, materials, stack-up, connectors, cables, transmitter/receiver packages, and other parasitic effects need to be considered This paper discusses the impact of via and more importantly the impact of via stub position and length on high speed serial links Via stub resonance impacts high speed signals but in this paper it is shown that their position also has an impact Depending on where the via stubs are located on a high speed channel, sometimes their effect could be insignificant (no eye degradation) and sometimes their impact could be significant (major eye degradation) High speed analysis is performed at 16Gbps and 20Gbps to demonstrate the margin loss due to various positions of via stubs

Modeling of Mixed CNT Bundle for Sub-threshold Interconnects

Abstract: In this paper, we report the analysis of Mixed Carbon nanotube bundle (MCB) as potential interconnects in the sub-threshold regime. MCBs with specific and random arrangement of non-identical MWCNT diameters are proposed. The sub-threshold crosstalk delay has been obtained analytically for different MCB arrangements and is compared with SPICE simulation results. It is found that there is significant improvement in crosstalk induced delay for MCB where SWCNTs are located in the centre while MWCNTs are at periphery in the bundle.

Crosstalk Analysis for Rough Copper Interconnects considering Ternary Logic

Abstract: In this paper, crosstalk induced effects in a 3-line bus architecture for global interconnects has been investigated. The dimensions of global level Copper (Cu) interconnects at 22nm technology node are taken as per ITRS. Crosstalk effects have been analyzed for both repeated and unrepeated lines in ternary logic. We have compared crosstalk performance and signal integrity metrics for Cu interconnects with rough as well as smooth surfaces considering Carbon Nanotube FET-based drivers and receivers at 22nm node in ternary logic. Our simulation results show that worst case crosstalk delay, power delay product and number of repeaters used in Cu interconnects with rough surfaces are significantly higher than smooth interconnects. Also, bandwidth density, eye height and width are considerably degraded due to roughness.

Wafer Quality Inspection using Memristive LSTM, ANN, DNN and HTM

Abstract: The automated wafer inspection and quality control is complex and time consuming task, which can be speed up using neuromorphic memristive architectures, as a separate inspection device or integrating directly into sensors. This paper presents the performance analysis and comparison of different neuromorphic architectures for patterned wafer quality inspection and classification. The application of non-volatile memristive devices in these architectures ensures low power consumption, small on-chip area scalability. We demonstrate that Long-Short Term Memory (LSTM) outperforms other architectures for the same number of training iterations, and has relatively low on-chip area and power consumption.

Prediction of IC Equivalent Magnetic Dipoles Using Deep Convolutional Neural Network

Abstract: The equivalent dipole model based on near electromagnetic field scanning can be used for electromagnetic interference sources reconstruction without considering the specific circuit structure. This paper presents a new method for predicting the equivalent magnetic dipole by deep convolutional neural network for simulation of IC electromagnetic radiation. The numerical testing results demonstrate that the equivalent magnetic dipole array predicted by CNN can produce the original radiation field effectively.

Multi-pin Optimization of Decoupling Capacitors on Practical Printed Circuit Boards

Abstract: A fast and efficient method is proposed for placement of decoupling capacitors on printed circuit boards (PCB) with resonant parallel planes Using the pin impedance as a fitness function, a genetic algorithm (GA) based method is used for simultaneous optimization of capacitors’ placement with respect to ball-grid array (BGA) pin fields The proposed method applies to practical PCB designs without restriction on the number of power pins or planar geometry The developed algorithm is tested on an industrial example in comparison to a numerical electromagnetic (EM) simulator The results are shown to agree well while significant speed-up is obtained with the proposed algorithm

Impact of SMT Connector Pads on High Speed Serial Links

Abstract: Connectors are needed when high speed serial links pass through multiple printed circuit boards (PCBs) or cables. Surface mount (SMT) connectors play an important role in improving signal integrity as signal speeds continue to increase. Orientation of SMT connector lead frame when mounting on the PCB pad determines the direction of the signal breakout. Improper breakout of the signal due to the via location or otherwise can create an unintentional stub at the connector pad that can impact signal quality. In this paper, the impact of SMT connector pad on high speed serial link is discussed along with some examples. Proper breakout from the connector can result in short pad stubs. In cases where proper breakout is not possible, via-in-pad design is proposed as an approach to mitigate the risk for high speed designs.

Variability-Aware Performance Assessment of Multi-Walled Carbon Nanotube Interconnects using a Predictor-Corrector Polynomial Chaos Scheme

Abstract: In this paper, a predictor-corrector scheme is presented to expedite the construction of polynomial chaos (PC) metamodels for the variability-aware performance assessment of multi-walled carbon nanotube (MWCNT) interconnects. The proposed scheme is broken into two main stages. First, a low-fidelity predictor PC metamodel of the MWCNT network is constructed using the equivalent single conductor (ESC) approximation model. Thereafter, the accuracy of the predictor model is sufficiently enriched using a low-order corrector function based on the rigorous multiconductor circuit (MCC) model. The combined CPU costs of constructing the predictor and corrector functions are 9 times smaller than the CPU costs for directly constructing a conventional PC metamodel of comparable accuracy.

A New Compact Dual-Polarized Integrated Antenna Array for 2G/3G/4G/LTE Base Station Applications

Abstract: A new compact dual-polarized integrated antenna base station (BS) array is proposed in this paper. It consists of one center linear arrays and two side one with their total size of only $356 \times 1000 \times 81\ \mathrm {mm}^{3}$. The center array is operated in full-band (0.69-0.96/1.7-2.7GHz) while the two sides arrays worked in high band (1.7-2.7GHz). The full-band elements are designed based on both our new high band feeding and low band (0.69-0.96GHz) Electromagnetic (EM) dipole techniques. The main performance features of the BS array, i.e., cross polarization discrimination (XPD) and 15 (11) dBi gains in their high (low) frequency band respectively, are fully designed and obtained by using simulations. The validities of the design are verified by the measurements, showing that the BS array have good potential applications in wireless BS.

Impact of MWCNT Radii on the Performance of Nano Regime Interconnects

Abstract: Carbon nanotube (CNT) has emerged as a potential alternative to Copper in the field of on-chip ULSI interconnects. This paper presents the radii impact on the performance of multiwalled CNTs (MWCNTs) at standard 14 nm technology node for a fixed area of 2916 nm2. The number of conduction channels decreases by 95.39% when MWCNT inner radius increases from 4nm to 26nm. This is due to the reduction in number of CNT shells. The effects of radii on MWCNT line parasitics, propagation delay, power, and power-delay product (PDP) are also presented. The average power reduction is observed to be 76.65%. The figure of merit i.e., PDP improves by 36.94%. The observed interesting behavior may incline the future research towards further overcoming the challenges posed by MWCNTs.

Extension of EMPSIJ for Estimating the Impact of Substrate Noise on Jitter in a CMOS Inverter

Abstract: This paper presents an analysis of jitter in a CMOS inverter due to power supply, ground bounce and substrate noise. The analysis is based on the recently introduced method EMPSIJ [1] which is extended in this paper for substrate noise induced jitter. To estimate jitter due to various noise sources (such as supply noise, ground bounce, substrate noise), noise transfer functions are derived. The results of EMPSIJ and the EDA simulations are compared for an inverter designed in a 28nm CMOS Technology of TSMC. For multiple test cases, the results match reasonably well with mean percentage error (MPE) not exceeding 10%.

Power Delivery Network Design Strategy for Next Generation High Speed IO

Abstract: Serial I/O (Input-Output) working at 12GHz and beyond demands more accuracy in decoupling solution and lesser IR drop and it’s more challenging in designing the PDN (Power Delivery Network) with multi power rails. This paper describes the challenges faced in PDN analysis and methodical ways in meeting the PDN design requirements, specification, deterministic jitter number and is validated with post silicon results. The key design challenges like isolating the power/ground planes with multiple power rails, selecting optimum VR (voltage regulator) sense-point to have minimum IR/DC (direct current) drop and modeling the explicit decoupling capacitors (decaps) with highest accuracy has been implemented.

A Quick Assessment of Nonlinearity in Power Delivery Networks

Abstract: A nonlinear analysis of a DC-DC buck converter is presented in context of its harmonics in a power delivery network (PDN). The closed-form relationships of the harmonic distortions associated with the DC-DC buck converter are derived by Volterra series to estimate the effects in a practical environment using S-parameters. For the validation of the proposed method, the buck converter is designed in a 180 nm LDMOS technology and three test cases are considered by using three different practical PDNs. A close matching is seen between the results obtained by proposed and conventional methods with a significant speedup reported.

Package Level Radio Frequency Interference Shielding Structure Using Via Array

Abstract: This paper proposes a via array structure that is applicable to package in reducing radio frequency interference (RFI). The via array structure is applied to the redistribution layer (RDL) of the package for shielding purposes. To further validate the effect, the test structure is designed and fabricated using Yagi-Uda antenna and microstrip mitred bend (MMB) transmission line. The coupling between the transmission line and embedded antenna is investigated to determine the strongest noise coupling point, and via array structures are placed at those points. By applying the proposed via array structure, the measured coupling noise between the transmission line and the receiver antenna is reduced up to 12 dB.

Comparison and Application of Two Approaches Extracting Equivalent Dipole Arrays of an IC from Measured Near-Field Magnitude Data

Abstract: Two approaches to extract equivalent dipole arrays of integrated circuits (ICs) from only magnitude information of near-field scanning data are compared and applied to a test IC. One approach is based on the nonlinear least square (NLS) fitting, and the other is extracting the dipoles from the complex field data after retrieving the field phases. Using a commercial simulation tool, the extracted dipole arrays are tested to estimate the fields caused by the IC with- and without-an additional shielding structure.

Simulation-Based Impedance Characterization of PDN in High-Performance Multi-Chip HTCC Packages for Avionics

Abstract: High-Speed Multi-Chip HTCC Packages for Avionics require careful considerations early in the design cycle to obtain the optimum electrical performance. Some design goals can be achieved with simple stackup or layout modifications, but others require a detailed analysis using electromagnetic field solvers [1]–[3]. This paper proposes a design methodology and various guidelines to meet the optimum electrical performance in terms of Power Integrity. The methodology presented here is based on different sections of power and ground net pairs and is supported by extensive simulation results.

Rational Function Approximation of Parallel Coupled line Interconnects in RF Applications

Abstract: This article presents the modeling of parallel coupled line interconnects in high speed RF applications. The modeling approach described in this paper generates a rational function representation of the coupled line interconnects. The model captures the significant electromagnetic effects between coupled line interconnects such as coupling and crosstalk which becomes prominent at higher frequencies. The model is also verified for different spacing between the coupled line interconnects. Further, the network equivalent of the model can be incorporated in any time domain system level simulations for more accurate studies and analysis.

LIM Algorithms for Diodes and Branch Capacitors

Abstract: The latency insertion method (LIM) has been demonstrated as an optimum algorithm for the transient simulation of large networks. However, several network topologies and circuit elements do not lead to a LIM-compatible formulation. This work addresses the derivation of LIM expressions for non-standard topologies and elements. In particular, we address the formulation for nonlinear elements and branch capacitors. Examples and comparisons are given for evaluating the algorithms.

A Methodology for distributed Co-design and Coextraction of Die Re-distribution Layer and Package

Abstract: A complete methodology for distributed co-design and co-analysis of Die Re-distribution layer with the package is developed and presented. A test chip is designed in a generic 65nm process with six metal layers out of which 3 layers of RDL have been exported to a Package design tool and placed on top of a four-layer flip-chip package. After successfully co-designing the RDL routes and bumps in conjunction with package routes, the three RDL layers were exported back to the IC design environment for final sanity checks. An S-parameter extraction on the combined geometry including RDL layers and Package layers is then carried out in an EM solver. It is shown that combined geometry s-parameter extraction on signal net was able to capture the resonance due to RDL and Package layer coupling at 1.9GHz as compared to when extraction was carried out only on Package geometry.

Study of Series-series Topology for Suppressing Electromagnetic Interference (EMI) for Digital TV Wireless Power Transfer (WPT) Systems

Abstract: In this paper, we have studied series-series (SS) topology and designed a band pass filter modified series-series (BF-SS) topology to reduce the electromagnetic interference (EMI) for a digital television (DTV) wireless power transfer (WPT) systems. The EMI is one of the most important and serious issue for the package system which degrades the performances of the electronic devices. The modified topology consists of a band pass filter in parallel and series of a load resistance (R L ) and a capacitance (C), respectively of a receiving (Rx) coil. Amalgamating the advantages of series-series topology, high efficiency in a small load system, and a band pass filter, filtering frequencies of useful range, our BF-SS topology has shown promising results in reducing EMI. By keeping 30 cm distance between a transmitting (Tx) coil and a Rx coil, 0.1 coupling coefficient, 145 kHz operational frequency, and $\mathrm {R} _{\mathrm {L}}\ 70\ \Omega $; we observed significant reduction in the 3rd, 5th and 7th Rx current harmonics using BF-SS topology by 6.93 dB, 17.05 dB and 17.23 dB respectively maintaining 150W load power. Moreover, we observed high coil to coil power transfer efficiency (PTE) of 96.03 % through BF-SS topology. This reduction of 3rd, 5 th and 7th Rx current harmonic reduces EMI interference.

Impact of Integrated Circuit Packaging on Synaptic Dynamics of Memristive Devices

Abstract: The memristor can be used as non volatile memory (NVM) and for emulating neuron behavior. It has the ability to switch between low resistance $R_{on}$ and high resistance values $R_{off}$, and exhibit the synaptic dynamic behaviour such as potentiation and depression. This paper presents a study on potentiation and depression of memristors in Quad Flat Pack. A comparison is drawn between the memristors with and without the impact of parasitics of packaging, using measured data and equivalent circuit models. The parameters in memristor and packaging models for the SPICE simulations were determined using measured data to reflect the memristor parasitics in Quad Flat Packs.

Analysis of electrical power in IBM POWER9 direct-attached memory subsystem

Abstract: POWER9 processors are the current generation IBM POWER processors supporting direct-attached memory on the POWER series server systems. The POWER9 processors supports Industry Standard Registered Dual In-line Memory Modules (IS-RDIMM) running with Double Data Rate Generation 4 (DDR4) technology for the single-drop and dual-drop memory configurations. Memory throttling is an important feature of IBM systems for generations, but for the first time through direct-attached DDR memory interface in POWER9. Discussed in this paper is a case-study of the different memory throttles, their direct impact on the overall memory bandwidth and finally, the estimation of power consumed by the memory subsystem on POWER9 systems. The memory subsystem power estimation and consumption study determine the system bulk power requirements, apply them to system firmware and finally the datacenter architecture for IBM’s customers.