Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2019"

Machine-Learning-Based Error Detection and Design Optimization in Signal Integrity Applications

Abstract: Evaluating the robustness of integrated circuits (ICs) against noise and disturbances is of crucial importance in signal integrity (SI) applications. In this paper, the addressed challenge is to build a software-based framework allowing for automated detection of failures and fast simulation-based evaluation of designs. In particular, these tasks are here addressed using anomaly detection (AD), a branch of machine learning (ML) techniques focused on identifying erroneous or deviant data. In the proposed framework, the ML model only requires the time-domain waveforms and no additional knowledge about the circuit nor about the errors to be identified. Specifically, a two-step approach to detect anomalous behaviors in output waveforms of digital ICs is proposed, comprising a first phase where the ML models are trained to learn relevant features describing the data and a second one where those features are used to identify anomalies with unsupervised or semisupervised AD techniques. Two relevant application examples validate the performance and flexibility of the proposed method.

Design of High-Speed Links via a Machine Learning Surrogate Model for the Inverse Problem

Abstract: This paper presents an alternative approach for the design of high-speed link based on a preliminary version of a surrogate model for the inverse problem. Specifically, given the overall structure of the link, our goal is to build an accurate and fast-to-evaluate model for the estimation of the geometrical parameters of its interconnect starting from the desired eye diagram characteristics. The modeling scheme proposed in this paper relies on a powerful machine learning regression technique such as the least-squares support vector machine (LS-SVM) which is used to provide an accurate relationship among the desired eye features and the geometrical parameters of the link interconnect. The proposed model is built from a set of training samples generated by a parametric simulation of the link through the full-computational model. The feasibility and the accuracy of the proposed modeling scheme are then investigated by comparing its predictions with the corresponding results provided by the full-computational model on 250 unseen samples.

Self-Decoupled, 5G NR77/78/79 Two-Antenna System for Notebook Computers

Abstract: In this paper, we demonstrate that two antennas not only share the same radiator but also are decoupled using the same. The design consists of two driven coupling strips and one parasitic loop. The common parasitic loop is shared by two antennas and coupled-fed by both coupling strips. The driven strip is able to generate a monopole mode at about 4.6 GHz while the parasitic loop provides a 1.0-λ loop resonance at about 3.4 GHz, together covering the 3.3–5.0 GHz wideband for the 5G new-radio (NR) bands 77/78/79. By introducing a capacitive load to the loop, the 1.5-λ loop resonance can be lowered to cancel out opposite-phased currents of the 1.0-λ loop on the half portion, leading to self-decoupled properties around 3.4 GHz. The results show that the mutual coupling can be reduced by about 13 dB. The proposed design occupies a compact size of 5 mm × 35 mm (about 0.05λ × 0.38λ at 3.3 GHz).

Supply Induced Aperture Uncertainty-Aware Target Impedance Methodology to Solve RFIC Receiver Design Challenge Based On PDN Analysis

Abstract: Chip-package-System co-design has been attracting attention recently as a design methodology in development. One of the most important elements is to present detailed analysis of supply induced aperture uncertainty of RFIC receiver analog front-end for signoff in frequency domain. With aperture uncertainty sensitivity extraction of RFIC receiver analog front-end block circuit (LNA/Mixer/DC offset cancellation/VGA/bandwidth filter/level shifter), it is possible to enable accurate aperture uncertainty-aware target impedance calculation. The goal during system-level design is to provide adequate performance at minimum cost while giving the in-depth SI/PI insight into RF analog front-end design field and achieving on system-level success.

Design of Wideband Functional Via Structures for LTCC Multilayer Substrates up to 110 GHz

Abstract: A novel concept for designing wideband via structures on low temperature cofired ceramic (LTCC) substrates is presented. In order to achieve wideband behavior, the vias have to be optimized with respect to frequency stability of the characteristic impedance so that the vias may be operated functionally as transmission lines. The characterisitc impedance and phase velocity of the via transition are studied through design space exploration involving critical parameters, i.e. antipad radius, distance to and number of ground vias, and cavity height. Typical LTCC technology constraints are observed in order to ensure manufacturability. Full wave models based on the finite element method (FEM) and finite integration technique (FIT) constitute the main computational tools for analysis and cross-checking of simulation results. Lastly, a sensitivity analysis is conducted to assess the applicability of vias as transmission lines in light of manufacturing tolerances. Parasitic effects due to microstrip or stripline connections are neglected in this work.

Bayesian Optimization for High-Speed Channel Equalization

Abstract: Equalization methods are used to recover the signal attenuated by channel loss. Different optimization algorithms are applied to find the best tap coefficients for each equalization that will improve eye opening and reduce bit error rate. The goal function for most equalization optimization algorithms is to reduce the difference between input and output signals, which is a linear optimization problem and can be solved relatively easily. This indirectly will increase eye height and improve eye diagram. Directly optimizing eye height is a non-linear problem and cannot be solved with analytical method. We are proposing FFE and DFE combined equalization optimization algorithm that optimizes directly eye height using Bayesian Optimization (BO). The proposed algorithm can be generalized for multi-level signals.

A mm-Wave Low-Loss Transition from Microstrip Line to Air-Filled Substrate Integrated Wavguide on Printed Circuit Board Technology

Abstract: This paper introduces the design of an air-filled substrate integrated waveguide (AFSIW), and a transition design from microstrip line (ML) to AFSIW at 60 GHz. The proposed structure is realized by printed circuit board (PCB) technology so that the fabrication cost is low and the whole structure is easy to be integrated with other planar components. An equivalent circuit model of the proposed ML-AFSIW transition is proposed and verified by full-wave simulation. To verify the proposed idea, a back-to-back transition is designed, fabricated and measured. The measured return loss is higher than 15 dB from 60.6 to 64.5 GHz. The minimum of measured insertion loss is 0.2 dB at 61 GHz. The measured results show that the proposed ML-AFSIW transition is suitable for millimeter-wave (mm-Wave) application.

Electrical and Thermal Co-Analysis of Thermally Efficient SiP for High Performance Applications

Abstract: Applications including artificial intelligence, 5G mobile communication, and virtual reality require a large amount of computations, wide bandwidth, and high-speed data transmissions with very low error levels. The system-in package (SiP) becomes a promising solution to satisfy those requirements. Not only the SiP has a smaller form factor, but also it provides improved signal integrity because the shorter channel length can be achieved. The decreased distance between the logic chips and the memories lower the insertion loss, the crosstalk level, and therefore the signal degradation can be minimized. However, a high level of the system integration in the SiP and the high computing performance can result in a poor thermal management. The high computing performance requires increasing the transistor densities in various IPs, and the switching speeds of the transistors. This leads to increased power consumptions, which cause large thermal dissipations. The thermal dissipations in the package aggravate transistor performance, which yields an overall performance degradation or system malfunctions. Using heat spreader or high thermal conductive material can mitigate the thermal issues, but they are insufficient solutions. In order to improve the thermal management in the SiP, a novel SiP structure is introduced. The proposed SiP has thermal dissipation paths, which is called thermal chimney, from logic/memory dies to the heat spreader. The thermal chimney is high thermal conductive material, and it establishes a direct channel for heat flowing from the chip to the heat spreader to reduce the temperature in the package. In this study, the thermally efficient SiP geometry, how it cools down the package temperature and the manufacturing process will be described. The electrical and thermal performance will be analyzed when assuming the SiP consists of modems and DRAM memories.

A Novel Dynamic PI Simulation Methodology Including Non-linear PMIC Characteristics for DDR5 Module

Abstract: With the ever-increasing demand for both highperformance and low-power memory modules, it is becoming more and more difficult to meet the SI/PI-related target specifications. This problem can be further aggravated as the supply voltage of Double Data Rate (DDR) memory module decreases from 1.2 V down to 1.1 V for DDR5, possibly resulting in more logic malfunctions of the system. In order to mitigate these problems, Power Management Integrated Circuit (PMIC) is adopted on the DDR5 module to enhance the PI performance. Accordingly, an accurate evaluation of its characteristics has become of utmost importance for prediction of module-level voltage ripple (AC) and IR drop (DC) characteristics. In this paper, a novel methodology for accurate analysis of module-level PI performance, which includes non-linear PMIC characteristics along with other power models of passive components and CPM, is proposed. Through a series of simulations in both time and frequency domains, we successfully verified the accuracy of the proposed methodology and proved its high practicality.

Power Integrity Comparison of Off-chip, On-interposer, On-chip Voltage Regulators in 2.5D/3D ICs

Abstract: Insatiable increase of power consumption of high performance computing, various types of workloads, and lowering supply voltage require a stable and rapidly responding power supply. Integrated voltage regulators (IVR) are considered and studied as a promising solution for the fine grain power supply. In this paper, we introduce an IVR on active interposer for high performance 2.5D/3D ICs and analyze the proposed IVR by comparison with off-chip and on-chip voltage regulators (VRs). The efficiency, transient response and power noise suppression effects of each VR are evaluated. By optimal design of 2-stage VR, the IVR scheme shows higher efficiency. As closer distance from VR to load, improved transient response and power noise suppression can be achieved. In addition, due to the integration of voltage regulator circuit on active interposer, the effective footprint of module with the proposed IVR is the smallest.

LTCC Dielectric Constant and Loss Tangent Extraction by Thru-Line Method in Stripline

Abstract: Stripline can support pure TEM mode propagation but its signal trace is embedded inside substrate. GSG probe pad, microstrip line and via transitions are designed to allow GSG probing on substrate surface to measure S-parameters of stripline. The mismatch of transitions are removed by thru-line method to yield complex propagation constant of stripline. As propagation constant is measured, the e r and tanδ of the substrate can be calculated by closed-form equations. Measurement results of a low e r and low loss LTCC substrate show that longer LINE circuits can give more stable results in e r and tanδ.

Dielectric Characterization of Printed Circuit Board by Microstrip Line Up to 110 GHz

Abstract: This paper presents the characterization method and the measurement result of the dielectric property for printed circuit boards (PCBs) by microstrip transmission lines (TLs), with the multiline thru-reflect-line (MTRL) calibration and the probing techniques for the scattering parameter (S-parameter) measurements. The broadband TL propagation constant is evaluated accurately after the MTRL calibration, and the characteristic impedance is further determined by an additional resistor test item with the low substrate loss assumption. The extraction of the dielectric constant (DK) for the PCB substrate then becomes an inverse problem where the estimated DK can determine the TL propagation constant which is compared to the measured data for modifying the DK; this process is proceeded iteratively until the error between calculated value and the measured one satisfying the criterion. The proposed method is examined by the NF30 substrate, in the frequency range from 1 GHz to 110 GHz.

Design and Measurement of a 28 GHz Glass Band Pass Filter based on Glass Interposers for 5G Applications

Abstract: In this paper, we design and measure 28 GHz band pass filter (BPF) based on glass interposer for 5G applications. We design the parallel coupled resonator BPF based on the glass interposer. To control the even- and odd mode characteristic impedance, we adopt the multi-layer ground. Also, to reduce the channel loss, the wide coupled channels for 28 GHz BPF are designed. Designed 28 GHz glass BPF was verified by simulation using the 3D-EM simulator. Also, Designed 28 GHz glass BPF was fabricated to verify the electrical performance through measurement. Simulated and measured insertion loss of the designed 28 GHz glass BPF is −2.4 dB and −3.4 dB at 28 GHz, respectively.

Estimation of Wirebonded Package Inductance and Resistance using Statistical DOE/RSM

Abstract: This paper presents a methodology for quick estimation of the parasitic inductance and resistance of the nets in a wire bonded ball grid array (BGA) package. The methodology is built on statistical Design of Experiment (DOE) using the Response Surface Method (RSM). It creates a model, a prediction formula, from a set of 3D electromagnetic (EM) simulations with different package parameter such as routing length, bond wire profile and bond wire length. For model validation, the estimated inductance and resistance were compared with results from actual EM simulations both using the same random set of parameter value combinations.

Multiphysics Approach Using Computational Fluid Dynamics for Signal Integrity Analysis in High Speed Serial Links

Abstract: Historically, signal integrity (SI) modeling and analysis was performed standalone without considering non-electrical aspects of the design. Going forward, this approach may not be viable to model high-speed serial links. Increased demand for higher CPU core count is resulting in higher wattage CPUs. This in-turn is increasing the number of phases of voltage regulator module (VRM) driving higher thermal footprint for the design. Increase in temperature impacts high-speed interconnect performance adversely. Modeling interconnects for worst-case operating temperature can be unrealistic and could lead to over-design of a channel. In this paper, a Multiphysics approach is proposed to model next generation high-speed interconnects. Computational fluid dynamics (CFD) is used to determine the temperature gradient in the channel and thermo-electrical co-analysis is proposed to accurately predict the interconnect signal integrity (SI) characteristics. A realistic test case is used to demonstrate the importance of proposed Multiphysics co-analysis for different data rates.

PCB Integrated Inductor Design Optimized and Electrical Performance Analysis for Power Module Development

Abstract: In this work, the vertical direction magnetic field design of a multi-spiral stacked inductors is presented. It will be easy to get better inductance value by covering magnetic material, due to stacking method enhances the inductance density of the inductor for a given area. This paper reports an optimization technique for design and implementation of the PCB inductors with magnetic material. The proposed scheme shows higher inductance and lower DC resistance value compared to the non-optimized.

High Q-factor 3D Solenoid Inductor on InFO Package for RF System Integration

Abstract: High Q-factor (quality factor) 3D solenoid inductor formed by RDL (redistribution layer) and copper via in the molding compound on InFO package was fabricated. The effect of the turns and cross sectional area on Q-factor is discussed. The 3D solenoid inductor with 3 turns achieves the Q-factor of 59 at 3GHz and 0.68× lower of resistance and 1.6× higher of Q-factor than 2D spiral inductor at the same inductance. The coupling between two closely placed inductors is also investigated and it is found that the coupling in orthogonal placement is 12 dB lower than that of in parallel placement. The sample was fabricated and measured. The measurement results agree with the simulation, indicating the feasibility of the 3D inductor on InFO package.

Power Delivery Network Step Load Response and 1 st Droop Formulation

Abstract: Power integrity design has been a challenging task especially with devices that high in power consumption but require high performance and with very tight voltage budgeting. Most of the time, the solution space is also limited by the product cost target. Designer will need to validate the power delivery network (PDN) performance with various design operation activities to identify the worst-case current profile. Step load current is one of the common profiles that is used to verify the PDN dynamic noise against the voltage specification. This paper introduces a formulation to estimate the PDN transient response to the step load current profile and the induced 1st droop voltage noise. It provides a quantitative model to analyze the PDN characteristic and its response with different step load bandwidth profile. PDN bandwidth metric is also introduced in the formulation to study the relationship with the step load bandwidth. The PDN step load response will be separated to resistive and reactive impedance response and as well the ripple from the LC oscillation. This serves as the dynamic voltage budgeting methodology with respect to 1st droop event to quantify the IR drop and ripple voltage noise budget across board, package and die to meet the product voltage specification.

High Performance Low Cost Package and Platform Design for 56G PAM4 SerDes

Abstract: This paper will walk-through the process and challenges of design and integration of 56G PAM4 PHY into a low cost SoC package and platform targeting 5G base stations market. In order to deliver best in class design and meet strict electrical compliance from both the SerDes designer and the IEEE802.3 standards, an amalgamation of signal integrity optimization techniques are addressed in this paper.

Novel Antenna-in-Package Design for Automotive Surround-View Radar Systems

Abstract: Ultra-short range radar sensing and 360° surround view is emerging. To meet the sensing application, a novel antenna-in-package design with enhanced isolation for automotive surround-view radar systems is proposed. The design is composed of arrays of folded dipole elements and two additional stubs, which can enhance measured isolation peak to be 43 dB. Details of the design and measured results are presented.

Fast and Accurate Deep Neural Network (DNN) Model Extension Method for Signal Integrity (SI) Applications

Abstract: In this paper, we first propose a fast and accurate deep neural network (DNN) model extension method for signal integrity (SI) applications. Reusing pre-trained weights of DNN model, the model can be extended when new training data are given. Instead of updating whole weights of DNN in traditional machine learning (ML) approaches, fine-tuning of a part of weights can accelerate training. For verification, we applied the proposed method to regression model of peak time domain reflectometry (TDR) impedance of through hole via (THV) and classification model of through silicon via (TSV) void defects. Training time of the proposed method were 0.3 s and 2.3 s respectively, which are 99 % and 82.3 % reduction compared to the traditional approach. Moreover, test accuracy of the proposed method achieved 99.2 % and 100 %, respectively.

Interleaved Power Transmission Line for Mitigation of Digital to RF De-sense

Abstract: The RF de-sense problem in wireless products becomes serious due to faster digital signals and minimal area in print circuit boards. Company always uses least layers and area of PCB to cost down, which means traditional electromagnetic interference (EMI) suppression methods being inappropriate. This paper proposes an interleaved power transmission line to suppress the noise due to magnetic coupling from power delivery system of digital circuits to RF components. It improves noise suppression by more than 20 dB, in only two layers PCB, with one power trace and three ground traces to replace conventional power trace in the same occupied area.

Sparsity Constrained Regression For High-Speed Signal Integrity Modeling

Abstract: High-speed signal integrity (SI) modeling usually involves modeling non-linear subsystems. Traditional approaches like response surface modeling (RSM), artificial neural networks (ANN) and support vector machine (SVM) suffer from two major issues. Either they don’t scale well when the number of dimensions or variables increase in the non-linear model or they are sensitive to the initial training data used to create the models. For example: RSM approach requires large design of experiments (DoE) when the number of variables increase. With ANN, the designer has to spend a lot of time tuning or optimizing the hyperparameters. In this paper, a new approach based on sparsity constrained regression (SCR) is proposed. This approach can scale even when the non-linear problem has large number of variables and it only has one hyper-parameter to tune making it easy to train and test. A test case based on printed circuit board (PCB) stack-up modeling is used in this paper to test the efficiency of SCR approach. The results are compared against traditional RSM and ANN approaches.

Enhanced Power and Signal Integrity Through Layout Optimization of High-Speed Memory Systems

Abstract: In this paper, a high-speed memory bus with non-ideal power/ground reference was analyzed. Noise from power planes and vias would couple to the double-data-rate (DDR) signals and impact signal quality. Several design parameters of the system structure were considered to improve the DDR signal quality. Parameters such as location of the signals, location of noise source and placement of decoupling capacitor are considered to reduce the noise coupling. With optimized parameters, the transfer impedance between the victim signal and noise source could be suppressed and the noise coupling can be reduced accordingly. Time domain eye-diagram plots of the DDR signal are also used to depict the signal quality.

Signal Integrity Analysis for Dual-Stripline Design

Abstract: In today’s PCB design, dual-stripline is gaining more popular as it provides more density for signal routing of little PCB thickness therefore thinner products. However, it is becoming more important to keep track of signal and power integrity issues brought by the convenience of dual-stripline structure. It is well known dual-stripline crosstalk would cause severe problems for signals, in addition, for power rails as well. It is important to predict the problem beforehands with simulation and avoid the troubleshooting and debugging. In this work, the investigation of dual-stripline design is studied to figure out signal-to-signal coupling. A comprehensive solution is provided for this convenient structure in both simulation and measurement manners.

Modeling, Simulation and Measurement of On-chip Interconnects with Extremely Thin Si Substrate for Flexible Electronics

Abstract: In this paper, on-chip interconnections with an ultra-thin silicon (Si) chip for flexible electronics is modeled and verified through 3D EM simulation and measurement. To achieve flexibility of the chip, we grind a Si substrate to 15 μm. When the Si substrate is extremely thin, the lossy Si substrate effect can be reduced. Moreover, we place a ground plane on the top of the Si substrate to further reduce the Si loss. The interconnection lines are designed with the HFSS 3D EM simulation by changing design variables with 50 ohm matching impedance. In addition, we conduct an equivalent circuit modeling of the interconnection line based on RLGC components. The insertion loss (S 21 ) result of the model is then verified with the simulation and measurement results when we ignore the effect of the Si substrate. Finally, the modeling result showed good correlation with the simulation and measurement. From the experiments, we conclude that the flexible chip can be modeled with the simple interconnection RLGC model when the Si thickness is extremely thin and well designed.

Design and Analysis of High-Definition Multimedia Interface Connectors considering Signal Integrity

Abstract: Recently, the market of the high quality audiovisual is increasing, so is the need for reliable multimedia interfaces. These interfaces are required for high data transfer to consumer appliances such as 4K, 8K TV’s, projectors, etc. In this paper, we have proposed the high speed connector to support a high data rate of 12 Gbps at the frequency of 12 GHz than the previous connector at the frequency 6 GHz. We have designed the connector by modifying the overall terminal structure i.e., shape, length, and thickness. We have also changed the material properties of its housing enclosure. The proposed connector have verified by 3D EM-simulation. Signal integrity (SI) analysis for insertion loss, attenuation-to-crosstalk ratio (ACR), and impedance matching have conducted. In conclusion, the proposed high-speed connector has enhanced electrical performances than that of the previous connector.

Ultra-Thin Capacitors based on Carbon nanofibers with Ultra-High Capacitance Density

Abstract: In this paper, we present the current state-of-the-art technology of solid-state capacitors based on carbon nanofibers (CNFs). Taking advantage of the large 3D surface featured by vertically aligned and tightly spaced carbon nanofibers directly grown on the capacitor’s electrode, capacitance densities in excess of 650 nF/mm2 have been achieved at a profile height of only 7 μm, when employing medium-k field dielectric materials such as HfO 2 and Al 2 O 3 , to form the MIM-like capacitors. The integrated capacitors were fabricated on high-resistive Si substrate, while employing fully CMOS compatible processes. For the devices with highest capacitance density, the leakage currents are typically below 0.01 nA/nF at 1V, while sustaining voltages up to 6 V as well as very good temperature and voltage stability. For the largest devices, the equivalent series resistance (ESR) and inductance (ESL) are as low as 60 mOhm and 6 pH, respectively, as well as very good temperature and voltage stability. The results of the extensive DC and RF characterizations strongly support the potential for CNF-based solid-state capacitors to compete with established high capacitance density technologies and are suitable both in integrated on-chip solutions as well as in discrete electronic applications at a minimal component volume.

Design and Characteristic Calibration of TEM Cell for IC Radiation EMC Test

Abstract: With the development of IC nano-meter technologies advancing toward higher operating frequencies and the trend of integrated various wireless communication systems for smart autonomous car, the self-driving system with highly integrated high-speed digital circuits and multi-radio modules are now facing the challenge from performance degradation by even more complicated platform EMI noisy environment. Thus the radiated EMC problem has become a crucial issue for IC adoption by automobile industry. Since TEM Cell could be used for EMI test (IEC 61967-2[1]) and EMS test (IEC 62132-2[2]) on chip or module level, we therefore design and investigate the structure of TEM cell and its characteristics for IC EMC test in this study. Finally, we will utilize the TEM cell designed in this study to measure the EMI emission generated from flash memory under different operation and working conditions.

Simulation of Reflection Noise in Small Single-end Serpentine Delay Line in A Practical Server PCB

Abstract: Far-end crosstalk is well known to contribute to the voltage drop in the TDR (time-domain reflection) waveform in a single-end serpentine delay line. However, for a small and practical single-end serpentine delay line in a practical Server PCB, both far-end crosstalk and corner-turn reflection contribute to the voltage drop in the TDR waveform, and corner-turn reflection is the greater contributor. This paper examines the effect of a 3D EM solver and circuit solver on the TDR waveform.