Showing papers presented at "European Microwave Integrated Circuit Conference in 2007"
26 Dec 2007
TL;DR: In this article, the authors developed a kW-class AlGaN/GaN HEMT pallet amplifier operating at S-band with output power of over 800 W, high linear gain of 13.6dB and high efficiency of 52% over the wide frequency range of 2.9-3.3 GHz.
Abstract: We developed a kW-class AlGaN/GaN HEMT pallet amplifier operating at S-band. The pallet amplifier consists of an internally partial-matched AlGaN/GaN HEMT optimized for S-band on a copper base with soft PC boards. The developed pallet amplifier showed excellent performance, which is output power of over 800 W, high linear gain of 13.6dB and high efficiency of 52% over the wide frequency range of 2.9-3.3 GHz, operating at 65 V drain voltage with the pulsed condition at a duty of 10% and a pulse width of 200 musec. With 80 V drain voltage operation the peak power reached to 1 kW with 49.5% drain efficiency and 14.1 dB linear gain at 3.2 GHz. To the best of our knowledge, this is the highest power pallet amplifier ever reported for S-band.
35 citations
26 Dec 2007
TL;DR: In this paper, a 60 GHz cascode amplifier in a 90 nm technology is described, which uses an interstage matching to increase the gain and to provide a better power match between the common source and the common-gate transistor of the cascode device.
Abstract: The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption
27 citations
17 Dec 2007
TL;DR: In this article, a new structure of pulse shrinking time-to-digital converter (TDC) with 20 ps resolution is presented, which is implemented in Infineon 0.13 mum CMOS technology.
Abstract: This paper presents a new structure of pulse shrinking time-to-digital converter (TDC) with 20 ps resolution which is implemented in Infineon 0.13 mum CMOS technology. The new interpolating multi-stage TDC with feedback loop and high speed counter accelerates the digitization of the input time interval and is appropriate as phase detector for phase locked loop application. The interpolated multi-stage structure efficiently saves the chip area and power consumption. Its Full-Scale-Range (FSR) is about 5000 ps and its differential linearity errors are less than 0.52 LSB.
27 citations
26 Dec 2007
TL;DR: In this paper, the design of a simultaneous dual-band high efficiency harmonic tuned power amplifier is presented, which operates at 2.45 Ghz and 3.3 GHz, and measured results shown a drain efficiency of 53% and 46%, with an output power of 33 dBm and 32.5 dBm at the two hard widths.
Abstract: In this contribution for the first time the design of a simultaneous dual band high efficiency harmonic tuned power amplifier is presented. The active device used is a GaN HEMT with 1 mm of gate periphery. The realised amplifier operates at 2.45 Ghz and 3.3 GHz, and the measured results shown a drain efficiency of 53% and 46%, with an output power of 33 dBm and 32.5 dBm at the two hard widths. A zero transmission condition has been obtained, resulting in a measured value of S21 lower than -15 dB at 2.8 GHz.
24 citations
26 Dec 2007
TL;DR: In this article, an AlGaN/GaN high electron mobility transistors (HEMTs) with combined two dies of 12 mm gate periphery exhibits output power of over 30 W with power added efficiency (PAE) of 12% under VDS = 30 V, CW operating condition at 14.25 GHz, and a gain compression level of 3 dB.
Abstract: AlGaN/GaN high electron mobility transistors (HEMTs) were developed for Ku-band applications. The operating voltage characteristics in CW operating conditions were investigated. The developed AlGaN/GaN HEMT with combined two dies of 12 mm gate periphery exhibits output power of over 30 W with a power added efficiency (PAE) of 12% under VDS = 30 V, CW operating condition at 14.25 GHz, and a gain compression level of 3 dB.
19 citations
26 Dec 2007
TL;DR: In this article, a 60W AlGaN/GaN HEMT with the operating frequency in X-band was presented. But the performance of the 60W HEMTs was not evaluated.
Abstract: In this paper, we report our result of a 60W AlGaN/GaN HEMT with the operating frequency in X-band. The device technology is extension of well-established Eudyna commercial L-/S-band AlGaN/GaN HEMT technology. The device shows output power of over 60W and a high linear gain of 9.6dB in wide frequency range of 9.5-10.5GHz, operating at 40 V drain bias voltage with the pulsed conditions at a duty of 10% with a pulse width of 100 musec. The results show the developed 60W AlGaN/GaN HEMT has high power capability covering practical frequency range for X-band high power applications with proven device technology.
17 citations
26 Dec 2007
TL;DR: A Field Programmable Gate Array (FPGA) based platform for prototyping digital predistortion (DPD) linearizers, and a scalable DPD architecture is proposed and implemented, giving an insight on actual development scenarios of DPD systems accounting for memory effects.
Abstract: This paper presents a Field Programmable Gate Array (FPGA) based platform for prototyping digital predistortion (DPD) linearizers, and a scalable DPD architecture is proposed and implemented. This architecture eases the process of meeting transmission linearity requirements, depending of the degree of impairments added by the transmitter chain, and enables a quick migration between different DPD schemes. Details on the internal DPD organization, reconfiguration abilities, as well as experimental results showing DPD linearization of a 10 W LDMOS RF power amplifier are provided, giving an insight on actual development scenarios of DPD systems accounting for memory effects.
15 citations
26 Dec 2007
TL;DR: In this paper, the vector sum method was used to achieve continuous phase and amplitude control of a millimeter-wave phase shifter with an insertion loss of 17 dB with 30-dB dynamic range from 40 to 75 GHz.
Abstract: The design and measurement results of a continuous amplitude/phase control CMOS MMIC are presented in this paper. This circuit uses the vector sum method to achieve continuous phase and amplitude control. The phase shifter demonstrates all continuous phase control and an insertion loss of 17 dB with 30-dB dynamic range from 40 to 75 GHz. The chip size is only 0.7 mm times 0.6 nm. To the best of the authors' knowledge, this circuit is the first demonstration of millimeter-wave phase shifters MMIC using the vector sum method, with the smallest chip size for all MMIC phase shifters and 360deg phase-control circuits in frequencies above 5 GHz reported to date.
15 citations
26 Dec 2007
TL;DR: In this article, a broadband GaN monolithic power amplifier covering the L to X bands is presented as is required for various applications in measurement set-ups and multi-band systems.
Abstract: A broadband GaN monolithic power amplifier covering the L to X bands is presented as is required for various applications in measurement set-ups and multi-band systems. It is based on 8 transistor cells with 4 times 50 mm gate width each following the distributed amplifier concept. The amplifier achieves 10 dB broadband small-signal gain and a 3 dB cut-off frequency of 11 GHz. The circuit delivers between 1.4 and 2.2 W over the bandwidth from 2 GHz up to 10 GHz. At the maximum output power a PAE higher than 20% is achieved.
14 citations
26 Dec 2007
TL;DR: In this article, the design of a cascode GaN/GaN HEMT cell dedicated to 4-18 GHz flip-chip distributed power amplifier is described. But the active device is a 8x50 mum AlGaN/GEMT grown on SiC substrate and the matching elements are composed of series capacitances on the gate of both transistors with additional resistances to insure stability and bias path.
Abstract: This paper reports on the design of a cascode GaN HEMT cell dedicated to 4-18 GHz flip-chip distributed power amplifier. The active device is a 8x50 mum AlGaN/GaN HEMT grown on SiC substrate. The GaN-based die which integrates the active cascode cell and its matching elements is flip-chipped via electrical bumps onto an AIN substrate. The matching elements of the balanced cascode cell are composed of series capacitances on the gate of both transistors with additional resistances to insure stability and bias path. The series capacitor on the gate of the 1st transistor is added for the distributed amplifier optimisation while the series capacitor on the gate of the 2 nd transistor is dedicated
14 citations
26 Dec 2007
TL;DR: In this article, a highly integrated quasi-millimeter wave receiver chip that integrates 22 circuits on a 3 x 2.3 mm chip using three-dimensional MMIC (3D-MMIC) technology is presented.
Abstract: A highly integrated quasi-millimeter wave receiver chip that integrates 22 circuits on a 3 x 2.3 mm chip using three-dimensional MMIC (3D-MMIC) technology is presented. The receiver MMIC operates with an LO signal in the 2.7-3.1 GHz range. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.4 GHz. It can use low-cost VCOs and demodulators in a 2-3 GHz frequency band. The power dissipation of the MMIC is only 450 mW. It also achieved low noise (3.4 dB) and high gain (41 dB) at 26 GHz. Furthermore, it achieved a high dynamic range using two step attenuators in the RF and IF frequency bands with a new built-in inverter using an N-channel depression FET.
26 Dec 2007
TL;DR: In this article, a large signal measurement set up and analysis technique is developed to characterize and model the dynamic I/V characteristic of a two-terminal double-barrier quantum well structure, the resonant tunnelling diode (RTD).
Abstract: A large signal measurement set up and analysis technique is developed to characterize and model the dynamic I/V characteristic of a two-terminal double-barrier quantum well structure, the resonant tunnelling diode (RTD). The devices investigated have been realized on InP-substrate using sub-micron process technology in order to minimize power dissipation for high-frequency applications. The process technology applied employs electron beam lithography for precise definition of critical structures and self aligned dry chemical mesa etching. The extraction of device parameters from measurements is presented together with a scaleable large-signal RTD model.
26 Dec 2007
TL;DR: In this paper, low-frequency measurements and comparative analysis of methods used for surface passivation of high resistivity silicon (HR-Si) are described and compared with a selection of samples with a layer of ferroelectric material.
Abstract: This paper describes low-frequency measurements and comparative analysis of methods used for surface passivation of high-resistivity silicon (HR-Si). A number of substrates are evaluated; n-type and p-type HR-Si, with and without surface passivation by means of polysilicon or Ar-ion implantation. Additionally, a selection of samples is prepared with a layer of ferroelectric material. Substrate characteristics are extracted from measurements of the samples, allowing comparison of passivation methods and evaluation of the influence of the ferroelectric film. The study shows all passivation methods successful in removing any bias-dependence of substrate properties. Further, the high-temperature processing of the ferroelectric film is observed increasing the extracted substrate conductivity by about 70% for the Ar-ion implanted samples, and about 50% for the p-type samples passivated by poly-Si. The effective substrate conductivity of the n-type samples passivated by RTA-crystallised poly-Si appears unaffected.
26 Dec 2007
TL;DR: In this article, an active downconverter for 60 GHz high-speed data communication RF front-ends is presented, which consists of a single balanced mixer with an on-chip balun for differential to single ended conversion.
Abstract: This work presents an active downconverter targeted for integration in 60 GHz high speed data communication RF front-ends. The designed downconverter has been realized in 0.25 mum SiGe BiCMOS technology with ft around 200 GHz. The downconverter consists of a single balanced mixer with an on-chip balun for differential to single ended conversion. High linearity and bandwidth are the main design goals rather than high gain. A clear-cut investigation of the applied bottom up design approach was presented with emphasis on modeling the critical on-chip signal path interconnects, matching and filtering components. The design and applied methodologies will be justified by comparing the measured and simulated performances. At 60 GHz an input 1-dB power compression of -5 dBm, 2.5 dB conversion gain and a gain variation around 2 dB from 50 to 70 GHz, are measured. Current consumption of the mixer core is 4.7 mA from a 3.3 V supply and the active chip area is 0.48 mm2.
17 Dec 2007
TL;DR: In this paper, the authors proposed a broadband low-noise amplifier with high linearity performance using a bias circuit with high impedance, which achieved an S21 of 20plusmn1 dB and an S11 of less than -9 dB.
Abstract: We propose a broadband low noise amplifier with high linearity performance. The amplifier achieves broadband, low noise performance and high linearity using a bias circuit with high impedance. The bias circuit consists of an inductor, a resistor, and a current source. The circuit obtains high impedance using a high resistive component. From 0.8 to 5 GHz, the low noise amplifier shows an S21 of 20plusmn1 dB and an S11 of less than -9 dB. The noise figure is 1.5-2.7 dB for frequencies from 0.5 to 5 GHz. The output 1-dB compression point at 2 GHz is +6.3 dBm.
17 Dec 2007
TL;DR: In this paper, a low noise amplifier (LNA) in a low cost 0.8 mum SiGe heterojunction bipolar technology (HBT) was designed and implemented.
Abstract: We present the design, implementation and measurement of a low noise amplifier (LNA) in a low cost 0.8 mum SiGe heterojunction bipolar technology (HBT). The measured noise figure is between 2.1 dB and 2.6 dB in the FCC-allocated bandwidth for ultra-wideband (UWB) systems. The circuit delivers 19.6 dB peak gain with gain variations of 1.3 dB within the entire band from 3.1 to 10.6 GHz. Broadband noise and power matching has been achieved with a cascode topology using resistive shunt feedback in combination with a diode DC level shifter. The measured input IPS is -14.1 dBm with 10.3 mA total current from a 3.5 V supply. All performance characteristics are comparable to the best reported UWB LNAs but come at a drastically smaller occupied die area of 0.13 mm2.
26 Dec 2007
TL;DR: It is shown how the adoption of a distributed instead of a lumped description leads to a more accurate equivalent-circuit-based electron device model.
Abstract: Electron device modelling requires the accurate identification of a suitable parasitic network accounting for the passive structures which connect the intrinsic electron device to the external world In conventional approaches, the parasitic network is described by a proper topology of lumped elements As an alternative, a distributed description of the parasitic network can be conveniently adopted In particular, the latter solution is the better choice when dealing with device scaling and very high operating frequencies In this paper the parasitic network is described by means of a suitable distributed network identified through electromagnetic simulations of the device layout It is shown how the adoption of a distributed instead of a lumped description leads to a more accurate equivalent-circuit-based electron device model The good scalability properties of the approach are also presented through experimental results
26 Dec 2007
TL;DR: In this article, the design and measurement of a SP6T GaAs pHEMT switch for Quad-Band GSM/EDGE Front-Ends is discussed, using a novel approach to reduce the generated harmonic levels at 3 V supply, 35 dBm drive and antenna VSWR of 5:1 down to -40 dBm, the lowest levels for the multi-mode multi-throw switches reported to date.
Abstract: In this paper the design and measurement of a high performance SP6T GaAs pHEMT switch for Quad-Band GSM/EDGE Front-Ends are discussed. The design uses a novel approach to reduce the generated harmonic levels at 3 V supply, 35 dBm drive and antenna VSWR of 5:1 down to -40 dBm, the lowest levels for the multi-mode multi-throw switches reported to date. Besides low harmonic performance, low TX insertion loss of below 0.5 dB at 2 GHz and RX insertion loss of below 1 dB at 2 GHz is achieved.
26 Dec 2007
TL;DR: In this paper, a 20 G sample/s Track and Hold Amplifier with 20 GHz large-input-signal bandwidth is designed and fabricated in 210 GHz-fT-InP-DHBT on a 1.6 x 1.4 mm2 chip.
Abstract: A fully differential 20 Gsample/s Track and Hold Amplifier with 20 GHz large-input-signal bandwidth is designed and fabricated in 210 GHz-fT-InP-DHBT on a 1.6 x 1.4 mm2 chip. Spectral measurements in track mode give an SNR, a THD, and a SFDR respectively of 65 dB, -38 dB and -38 dB for input frequency up to 9 GHz and input voltage up to 0.5 Vpp. This THD is equivalent to 6 ENOB. Time domain measurements illustrate 20 GHz sampling with 2 and 5 GHz sinusoidal input signals.
26 Dec 2007
TL;DR: In this article, a protection circuit is developed which protects transistors in the output stage of a high power amplifier against voltage breakdown as a result of mismatch, which is applied in an S-band and X-band High Power Amplifier and measured under various mismatch conditions.
Abstract: A protection circuit is developed which protects transistors in the output stage of a high power amplifier against voltage breakdown as a result of mismatch. The circuit is applied in an S-band and X-band High Power Amplifier and measured under various mismatch conditions. The devices have been developed in the 6-inch 0.5 mum GaAs power pHEMT process (PP50-11) of WIN Semiconductors.
IBM1
TL;DR: Feasibility of wideband on-chip RF switch operating at millimeter wave frequencies using PIN diodes in IBM .13 mum SiGe technology is demonstrated and good correlations between simulation and hardware are reported.
Abstract: Feasibility of wideband on-chip RF switch operating at millimeter wave frequencies using PIN diodes in IBM .13 mum SiGe technology is demonstrated. A SPDT reflective switch targeting 60 GHz wireless and radar applications is designed, fabricated, and measured. Good correlations between simulation and hardware are reported. Measured data show 2.0 to 2.7 dB of insertion loss over 51 to 78 GHz bandwidth with better than 12 dB return loss and 25 to 35 dB of isolation.
26 Dec 2007
Abstract: This paper presents a design method for voltage controlled oscillators (VCOs) with simultaneous small size, low phase noise, DC power consumption and thermal drift. We show design steps to give good prediction of VCO phase noise and power consumption behavior: (1) measured resonator frequency-dependent parameters; (2) transistor additive phase noise/ noise figure characterization; (3) accurate tuning element model; and (4) bias-dependent model in case of an active load. As an illustration, the design of a 3.4-GHz bipolar transistor VCO with varactor tuning is presented Oscillator measurements demonstrate low phase noise (-40dBc@ 100Hz and better than -lOOdBcfflOkHz) with power consumption on the order of a few milliwatts with a circuit footprint smaller than 0.6cm2. The temperature stability is found to be better than +/-10ppm/degC from -40degC to +30degC. The oscillators are implemented using low-cost off-the-shelf surface-mountable components, including a micro-coaxial resonator. The VCO directly modulates the current of a laser diode and demonstrates a short-term stability 2-10/radictau Bias of clock. when locked to a miniature Rubidium atomic clock.
26 Dec 2007
TL;DR: In this article, two common topologies employing either two non-correlated noise-current sources, or a noisevoltage and a noisecurrent source, were analyzed and experimentally compared for the example of a GalnP/GaAs HBT.
Abstract: Although the shot-noise sources in bipolar transistors are strongly correlated, it is highly desirable for several reasons to rely on an approximative model that requires only noncorrelated sources. The two common topologies employing either two noncorrelated noise-current sources, or a noise-voltage and a noise-current source, are analytically analyzed and experimentally compared for the example of a GalnP/GaAs HBT. Differences and limitations of the two models are discussed, and it is shown how the topology can be modified in order to formulate a model based on noncorrelated sources that is accurate up to the transit frequency.
26 Dec 2007
TL;DR: In this article, a procedure to extract temperature dependent equivalent circuits for modeling the small and large signal behavior of GaN HEMTs is presented, using pulsed I-V measurements to obtain the temperature dependence of the parameters describing the nonlinear drain current source behavior.
Abstract: In this paper a procedure to extract temperature dependent equivalent circuits for modeling the small and large signal behavior of GaN HEMTs is presented. The technique explained in this work uses pulsed I-V measurements to obtain the temperature dependence of the parameters describing the nonlinear drain current source behavior. The equivalent circuits extracted are capable of correctly modeling the DC, small signal and large signal characteristics of GaN HEMTs devices. Simulations and measurements carried out on three transistors developed by SELEX-SI are compared over a wide range of frequencies, bias and load conditions.
26 Dec 2007
TL;DR: This paper presents advances in techniques for representing OFDM signals in nonlinear RF power amplifier behavioural modelling and compares accuracy, preservation of modulation information, complexity and computer resource consumption.
Abstract: This paper presents advances in techniques for representing OFDM signals in nonlinear RF power amplifier behavioural modelling. OFDM is significantly sensitive to nonlinear distortion because of the high peak to average power ratio (PAPR) of its envelope. Four signal representation techniques are presented and compared. These are direct time domain method (DTD), mixed frequency and time domain method (MFTD), statistical approach (stat), and MFTD combined with a modified stat approach (MFTD-MS). AH four are applied to a Bessel Fourier behavioural model for a GaN nonlinear PA. This model is a particularly suitable tool for large dynamic range nonlinearity analysis of certain classes of multicarrier signals. The goal is to compare accuracy, preservation of modulation information, complexity and computer resource consumption.
26 Dec 2007
TL;DR: In this article, a simple model of FET trapping based on a study of HEMTs using pulse techniques is presented, which accounts for the observed variation of extent of gate lag with bias and step potentials, and the variation of gatelag time constant with drain potential.
Abstract: We present a novel and simple model of FET trapping based on a study of HEMTs using pulse techniques. This model accounts for the observed variation of extent of gate lag with bias and step potentials, and the variation of gate-lag time constant with drain potential. Because both charge capture and emission are accounted for, the model is appropriate for the simulation of both large-signal and small-signal dynamics. The model is verified by comparison with large-signal transient measurements and is consistent with small-signal gain measurements.
26 Dec 2007
TL;DR: A state-space modelling technique using an artificial neural network (ANN) is used in this work to model the large signal behaviour of the GaN device, and the good agreement between measurements and simulation results verifies the proposed approach.
Abstract: GaN field effect transistors (FETs) have a strong potential for high-power applications. However the RF performance of these devices often experiences limitation due to trapping effects and self-heating. These complicate the development of accurate large-signal models for GaN FETs. To simplify this process, a state-space modelling technique using an artificial neural network (ANN) is used in this work to model the large signal behaviour of the GaN device. In this way, the model is constructed directly from large-signal measurement data collected while the device is in an operating mode close to its application, i.e., class AB power amplifier (PA). To demonstrate the approach, a hybrid power amplifier based on GaN FETs was designed and fabricated. The good agreement between measurements and simulation results verifies the proposed approach. It is the first time that this modelling approach is used in circuit design.
26 Dec 2007
TL;DR: In this paper, a SiGe sub-harmonic down-conversion mixer using a novel active anti-parallel diode pair is presented for millimeter-wave applications, which can help reduce conversion loss and also lower the required local oscillator power.
Abstract: A SiGe sub-harmonic down-conversion mixer using a novel active anti-parallel diode pair is presented for millimeter-wave applications. The proposed architecture can help reduce conversion loss and also lower the required local oscillator power. With an LO power of 0 dBm, the measured 2times conversion gain varies from -5 to -7.8 dB in the 50 to 65 GHz range. Compared to earlier reports of millimeter-wave SiGe and GaAs sub-harmonic mixers requiring 5 to 10 dBm of LO power, this circuit achieves similar conversion loss with an LO power as low as -7.5 dBm, while consuming only 0.5 mW of DC power.
26 Dec 2007
TL;DR: In this article, an active dual-stage high power S band limiter was designed using an accurate nonlinear PIN diode model that has been used to predict the limiter performances.
Abstract: This paper deals with the simulation and the design of an active dual stage high power S band limiter. The contribution of this work relies on an accurate nonlinear PIN diode model that has been used to predict the limiter performances. This model takes into account recombination phenomenon in the heavily doped region and include junctions effects. In the first section, the model is presented and validated by measurement results on two thin diodes. In the second section, the limiter output power and isolation characteristics are validated by power measurements up to +55 dBm and by spectrum measurements.
26 Dec 2007
TL;DR: In this paper, a fully differential low noise amplifier based on a classical cascode topology enhanced with noise cancelling technique is presented, which achieves a 0.1-1.7 GHz bandwidth.
Abstract: In this paper, a fully-differential low noise amplifier based on a classical cascode topology enhanced with noise cancelling technique is presented. This circuit achieves a 0.1-1.7 GHz bandwidth. The chip surface is less than 0.8 mm2. Measured circuit gain is greater than 18 dB and the 3 dB bandwidth is reached for a frequency of 18 GHz. The achieved noise figure is as low as 1.1 dB at 250 MHz and is lower than 1.3 dB all over the passband. This chip has been implemented using NXP QUBlC4G SiGe BiCMOS process.