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Conference

International Meeting for Future of Electron Devices, Kansai 

About: International Meeting for Future of Electron Devices, Kansai is an academic conference. The conference publishes majorly in the area(s): Thin film & Thin-film transistor. Over the lifetime, 437 publications have been published by the conference receiving 725 citations.

Papers published on a yearly basis

Papers
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Proceedings Article
01 May 2012
TL;DR: In this paper, the physics and basic properties of junctionless transistors are described and compared to devices with junctions, including excellent sub-threshold slope and DIBL, and they are shown to be less subject to short-channel effects than devices with junction.
Abstract: This paper describes the physics and basic properties of junctionless transistors. These FETs are less subject to short-channel effects than devices with junctions, including excellent subthreshold slope and DIBL.

50 citations

Journal ArticleDOI
04 Jun 2015
TL;DR: In this article, the authors investigated the characteristics of perovskite solar cells under low illuminance condition for indoor application of solar cells and showed that the open-circuit voltage remained around 70% at 0.1% of AM1.5.
Abstract: In this study, we investigated the characteristics of perovskite solar cells under low illuminance condition for indoor application of perovskite solar cells. The open-circuit voltage remained around 70% at 0.1% illuminance of AM1.5. This result indicates the potential for indoor application of perovskite solar cells.

42 citations

Proceedings ArticleDOI
26 Jul 2004
TL;DR: Experimental results on a biased 8-bit microprocessor, as well as unbiased MOSFETs embedded in a test element group (TEG) are reported.
Abstract: The inspection and fault analysis of semiconductor devices has become a critical issue with increasing demands for quality and reliability in circuits as stated in L. A. Krauss et al. (2001), K. Nikawa (2002) and K. Nikawa et al. (2003). Recently, we have developed a laser-terahertz (THz) emission microscope (LTEM) that can be applied for the noncontact and nondestructive inspection of the electrical faults in circuits presented in K. Nikawa et al. (2003). The LTEM can image the amplitude profile of the THz wave emitted by scanning the sample with femtosecond (fs) laser pulses. The amplitude of the THz emission generated by the transient photocurrent is proportional to the local electric field at the laser-irradiated area according to T. Kowa et al. (2003). Therefore, the LTEM image of the semiconductor device while it operates reflects the electric field distribution in the chip. By comparing the LTEM image of a damaged chip with that of a normal one, we can localize the electrical faults. In this work, we report experimental results on a biased 8-bit microprocessor, as well as unbiased MOSFETs embedded in a test element group (TEG).

23 citations

Proceedings ArticleDOI
09 May 2012
TL;DR: In this paper, the present status of Ge MOSFET technology, particularly focusing on n-FETs in terms of materials science of GeO 2 /Ge gate stacks and inversion layer mobility, is discussed.
Abstract: This paper overviews the present status of Ge MOSFET technology, particularly focusing on n-FETs in terms of materials science of GeO 2 /Ge gate stacks and inversion layer mobility, and then discusses future prospects and fundamental challenges from the viewpoint of new types of Ge FETs.

17 citations

Proceedings ArticleDOI
05 Jun 2013
TL;DR: In this article, a new SiC MOSFET structure with both gate and source trenches is presented, which greatly reduces device on-resistance while preventing oxide destruction at the gate trench bottoms.
Abstract: SiC Power devices are expected to greatly improve the efficiencies and operating capabilities of next generation electric and hybrid electric vehicles. The use of these devices allows for drastic size and weight reduction at the module and system levels of motor drives used in automotive applications. A new SiC MOSFET structure with both gate and source trenches is presented. This greatly reduces device on-resistance while preventing oxide destruction at the gate trench bottoms. Finally new packaging methods under development are outlined that take advantage of the benefits these new devices have to offer by transfer molding them in a high temperature resistant epoxy resin. This leads to modules with low thermal resistance and high power density that, when configured as a three phase inverter, reduce total system footprint and parasitic inductance.

16 citations

Performance
Metrics
No. of papers from the Conference in previous years
YearPapers
202221
201912
201833
201741
201643
201549