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International Solid-State Circuits Conference

About: International Solid-State Circuits Conference is an academic conference. The conference publishes majorly in the area(s): CMOS & Amplifier. Over the lifetime, 8795 publication(s) have been published by the conference receiving 275787 citation(s).

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Topics: CMOS, Amplifier, Phase-locked loop ...read more
Papers
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Journal ArticleDOI: 10.1109/4.482187
Asad A. Abidi1Institutions (1)
15 Feb 1995-
Abstract: Direct-conversion is an alternative wireless receiver architecture to the well-established superheterodyne, particularly for highly integrated, low-power terminals. Its fundamental advantage is that the received signal is amplified and filtered at baseband rather than at some high intermediate frequency. This means lower current drain in the amplifiers and active filters and a simpler task of image-rejection. There is considerable interest to use it in digital cellular telephones and miniature radio messaging systems. This paper briefly covers case studies in the use of direct-conversion receivers and transmitters and summarizes some of the key problems in their implementations. Solutions to these problems arise not only from more appropriate circuit design but also from exploiting system characteristics, such as the modulation format in the system. Baseband digital signal processing must be coupled to the analog front-end to make direct-conversion transceivers a practical reality.

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Topics: Radio receiver design (64%), Baseband (61%), Digital radio (60%) ...read more

1,051 Citations


Journal ArticleDOI: 10.1109/JSSC.1996.542317
01 Nov 1996-
Abstract: Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.

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Topics: PLL multibit (62%), Jitter (58%), Phase-locked loop (57%) ...read more

996 Citations


Journal ArticleDOI: 10.1109/4.881202
07 Feb 2000-
Abstract: The microprocessor system in portable electronic devices often has a time-varying computational load which is comprised of: (1) compute-intensive and low-latency processes, (2) background and high-latency processes, and (3) system idle. The key design objectives for the processor systems in these applications are providing the highest possible peak performance for the compute-intensive code (e.g., handwriting recognition, image decompression) while maximizing the battery life for the remaining low performance periods. If clock frequency and supply voltage are dynamically varied in response to computational load demands, then energy consumed per process can be reduced for the low computational periods, while retaining peak performance when required. This strategy, which achieves the highest possible energy efficiency for time-varying computational loads, is called dynamic voltage scaling (DVS).

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991 Citations


Journal ArticleDOI: 10.1109/JSSC.2006.886567
Reid R. Harrison1, P.T. Watkins1, R.J. Kier1, R.O. Lovejoy1  +3 moreInstitutions (1)
26 Dec 2006-
Abstract: Recent work in field of neuroprosthetics has demonstrated that by observing the simultaneous activity of many neurons in specific regions of the brain, it is possible to produce control signals that allow animals or humans to drive cursors or prosthetic limbs directly through thoughts. As neuroprosthetic devices transition from experimental to clinical use, there is a need for fully-implantable amplification and telemetry electronics in close proximity to the recording sites. To address these needs, we developed a prototype integrated circuit for wireless neural recording from a 100-channel microelectrode array. The design of both the system-level architecture and the individual circuits were driven by severe power constraints for small implantable devices; chronically heating tissue by only a few degrees Celsius leads to cell death. Due to the high data rate produced by 100 neural signals, the system must perform data reduction as well. We use a combination of a low-power ADC and an array of "spike detectors" to reduce the transmitted data rate while preserving critical information. The complete system receives power and commands (at 6.5 kb/s) wirelessly over a 2.64-MHz inductive link and transmits neural data back at a data rate of 330 kb/s using a fully-integrated 433-MHz FSK transmitter. The 4.7times5.9 mm2 chip was fabricated in a 0.5-mum 3M2P CMOS process and consumes 13.5 mW of power. While cross-chip interference limits performance in single-chip operation, a two-chip system was used to record neural signals from a Utah Electrode Array in cat cortex and transmit the digitized signals wirelessly to a receiver

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Topics: Sensor array (53%), Low-power electronics (52%), Electrode array (52%) ...read more

913 Citations


Proceedings ArticleDOI: 10.1109/ISSCC.2014.6757323
Mark Horowitz1Institutions (1)
06 Mar 2014-
Abstract: Our challenge is clear: The drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. Continuing to scale compute performance will require the creation and effective use of new specialized compute engines, and will require the participation of application experts to be successful. If we play our cards right, and develop the tools that allow our customers to become part of the design process, we will create a new wave of innovative and efficient computing devices.

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900 Citations


Performance
Metrics
No. of papers from the Conference in previous years
YearPapers
2021205
2020210
2019204
2018216
2017212
2016211

Top Attributes

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Conference's top 5 most impactful authors

Anantha P. Chandrakasan

64 papers, 4.8K citations

Kofi A. A. Makinwa

57 papers, 1.8K citations

Dennis Sylvester

51 papers, 2.4K citations

David Blaauw

50 papers, 2.7K citations

Hoi-Jun Yoo

44 papers, 1.9K citations

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