International Symposium on Plasma Process-Induced Damage 

About: International Symposium on Plasma Process-Induced Damage is an academic conference. The conference publishes majorly in the area(s): Gate oxide & Plasma processing. Over the lifetime, 356 publications have been published by the conference receiving 1329 citations.

Interconnect limits on gigascale integration (GSI)

Abstract: Summary form only given. Throughout the past four decades, silicon semiconductor technology has been advancing at exponential rates in both productivity and performance. In the physical world, such exponential advances cannot continue endlessly. A systematic assessment of early 21st century opportunities for GSI reveals an increasingly troublesome dichotomy. As minimum feature sizes continue to scale to ever smaller dimensions, transistor switching delay diminishes continuously while interconnect latency increases monotonically. The impact of this dichotomy can be moderated significantly by: (1) new materials and processes to reduce interconnect conductor resistivity and insulator permittivity; (2) reverse or smart scaling that optimizes the architecture of a multilevel wiring network to satisfy a complete set of performance specifications; and (3) new chip microarchitectures and instruction set architectures that serve to keep interconnects short and use longer interconnect paths more judiciously. Smart scaling of global interconnects for a system-on-a-chip (SOC) entails an integrated approach to design of the signal, power, and clock distribution networks. The projected performance of a SOC benefits significantly from novel high density, low cost, compliant lead input/output interconnect technology. Finally, 3D structures including multiple levels of transistors and interconnects provide an opportunity for reducing the length of the longest SOC interconnects and hence increasing global clock frequency.

Effect Of MOS Device Scaling On Process Induced Gate Charging

Abstract: Plasma induced gate charging damage is evaluated for advanced processes with ultra thin oxides. It is found that thinning the gate oxide results in increased damage up to a point. Beyond thiat, damage is reduced significantly due to direct tunneling current. Additionally, it is shown that diodes with breakdown voltages higher than oxide breakdown still offer protection against damage (piroportional to their area) while gated diodes offer improved protection. Elevated temperature during charging has been found to increase oxide degradation and PMOS structures have been found much more susceptible. Physical models are provided for these findings.

Plasma Charging Damage: An Overview

Abstract: Introduction Plasma processing has become an integral part of the fabrication of integrated circuits since it offers advantages in terms of directionality, low temperature and process convenience. However., plasma processing also offers increased damage potential because of surface charging of floating gates in MO!; devices. With the continued decrease in gate oxide thickness to improve device performance, this type of damage is becoming more of a concern. The damage can degrade all the electrical properties of a gate oxide which include the fixed oxide charge density, the interface state density, the flat band voltage, the leakage cui-rent and the various breakdown related parameters. [1,;!,17] As expected, all the MOS transistor parameters which depend on the oxide properties can be degraded by charging. [3]

Topographical dependence of charging and new phenomenon during inductively coupled plasma (ICP) CVD process

Abstract: This paper presents the influence of topographical parameters such as antenna area, perimeter and aspect ratio, on charging during an ICP oxide deposition process We show that an extended electron-shading occurs during the beginning of the deposition Moreover, we present a new phenomenon of drastic damaging when thin oxide layers are deposited We attribute this to an electron current transient at the wafer dechuck in the ICP chamber

Is NMOSFET Hot Carrier Lifetime Degraded By Charging Damage

Abstract: Introduction In CMOS technology, NMOSFET hot carrier lifetime is a more serious reliability issue than PMOSFET hot carrier lifetime. In an earlier paper[l], we reported an exponential relationship between NMOSFET hot carrier lifetime and plasma charging damage. Two groups[2, 31 had also looked at the same problem and found no correlation. A recent report[4], however, agree with our finding that charging damage do degrade the NMOSFET hot carrier lifetime. In this paper, we present data to show that both results are correct. Each is one side of a two faced coin. Whether or not charging damage impacts NMOSFET hot carrier lifetime depends on the polarity of the current flow during damage. If the current flow is gate injection, there is no correlation. If the current flow is substrate injection, there is an exponential correlation.