scispace - formally typeset
Search or ask a question
Conference

Radio Frequency Integrated Circuits Symposium 

About: Radio Frequency Integrated Circuits Symposium is an academic conference. The conference publishes majorly in the area(s): CMOS & Amplifier. Over the lifetime, 2688 publications have been published by the conference receiving 41736 citations.


Papers
More filters
Journal ArticleDOI
05 Apr 2011
TL;DR: Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived and the behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements.
Abstract: A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, P1dB=2 dBm and the noise figure is 3-5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).

378 citations

Journal ArticleDOI
06 Jun 2004
TL;DR: In this paper, a modified derivative-superposition (DS) method was proposed to increase the maximum IIP3 at RF frequencies, which was used in a 0.25mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple access receivers.
Abstract: Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP3 in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP3 at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP3 with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption

366 citations

Journal ArticleDOI
03 Jun 2007
TL;DR: A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented and is demonstrated to have a minimum internal gain of 14.5 dB.
Abstract: A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage.

363 citations

Journal ArticleDOI
24 Apr 2006
TL;DR: Implementation of floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications.
Abstract: This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.

340 citations

Journal ArticleDOI
24 Apr 2006
TL;DR: This paper focuses on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design, and identifies a new dissipative mechanism, peculiar of the cascode implementation, and proposes a circuit solution to minimize its effect.
Abstract: Power efficiency in switched common source class-E amplifiers is usually obtained at the expense of device stress. Device stacking is a viable way to reduce voltage drops across a single device, improving long-term reliability. In this paper, we focus on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design. In particular, a new dissipative mechanism, peculiar of the cascode implementation, is identified and a circuit solution to minimize its effect is proposed. Prototypes, realized in a 0.13-/spl mu/m CMOS technology demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth was also realized with greater than 60% PAE over the frequency range of 1.4-2 GHz.

186 citations

Performance
Metrics
No. of papers from the Conference in previous years
YearPapers
202287
202160
202094
201985
201889
2017104