Showing papers presented at "Southern Conference Programmable Logic in 2011"

A suitable FPGA implementation of floating-point matrix inversion based on Gauss-Jordan elimination

Abstract: This work presents an architecture to compute matrix inversions in a hardware reconfigurable FPGA with single-precision floating-point representation, whose main unit is the processing component for Gauss-Jordan elimination. This component consists of other smaller arithmetic units, organized to maintain the accuracy of the results without the need to internally normalize and de-normalize the floating-point data. The implementation of the operations and the whole unit take advantage of the resources available in the Virtex-5 FPGA. The performance and resource consumption of the implementation are improvements in comparison with different more elaborated architectures whose implementations are more complex for low cost applications. Benchmarks are done with solutions implemented previously in FPGA and software, such as Matlab.

Python as a hardware description language: A case study

Abstract: Many people may see the development of software and hardware like different disciplines. However, there are great similarities between them that have been shown due to the appearance of extensions for general purpose programming languages for its use as hardware description languages. In this contribution, the approach proposed by the MyHDL package to use Python as an HDL is analyzed by making a comparative study. This study is based on the independent application of Verilog and Python based flows to the development of a real peripheral. The use of MyHDL has revealed to be a powerful and promising tool, not only because of the surprising results, but also because it opens new horizons towards the development of new techniques for modeling and verification, using the full power of one of the most versatile programming languages nowadays.

A reconfigurable GF(2 M ) elliptic curve cryptographic coprocessor

Abstract: Elliptic Curve Cryptography (ECC) is a kind of cryptography that provides the security information services using shorter keys than other known public-key crypto-algorithms without decreasing the security level. This makes ECC a good choice for implementing security services in constrained devices, like the mobile ones. However, the diversity of ECC implementation parameters recommended by international standards has led to interoperability problems among ECC implementations. This work presents the design and implementation results of a novel FPGA coprocessor for ECC than can be reconfigured at run time to support different implementation parameters and hence, different security levels. Regardless there are several related works in the literature, to our knowledge this is the first ECC coprocessor that makes use of a partial reconfigurable methodology to deal with interoperability problems in ECC. A suitable application of the proposed reconfigurable coprocessor is the security protocol IPSec, where the domain parameters for ECC-based cryptographic schemes, like digital signature or encryption, have to be negotiated and agreed upon by the communication partners at run time.

Multichannel SDRAM controller design for H.264/AVC video decoder

Abstract: Embedded consumer electronics like video processing systems require large storage capacity and high bandwidth memory access. Also, those systems are built from heterogeneous processing units, designed specifically to perform dedicated tasks in order to maximize the processing power. A single off-chip memory is shared between the processing units to reduce power and save costs. The external memory access is the system bottleneck when decoding high definition video sequences in real time. This paper presents the design and validation of a multichannel DDR2 SDRAM controller design for a H.264/AVC video decoder. A four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The proposed controller is able to manage memory access in decoding 1080p H.264 video sequences. This architecture was validated and prototyped using a Xilinx Virtex-5 FPGA board.

Intelligent FPGA based system for shape recognition

Abstract: Mathematical morphology supplies powerful tools for low level image analysis, with applications in many areas. In this paper, the development of a novel reconfigurable hardware using a genetic algorithm and a pipeline architecture is proposed for the task of shape recognition in binary images. For the recognition process, a large sized convex structuring element representing the object shape to be recognized is decomposed into the architecture stages. Each stage can handle structuring elements of a limited size. In this approach, a genetic algorithm was used to decompose this structuring element. Thus, a simple erosion performed in each stage is used to detect the goal object. The hardware is capable of processing binary images at high speed. The developed system is based on FPGAs. Our approach represents an intelligent mechanism to reconfigure the pipeline architecture, it is different from other systems found in the literature, and the obtained results are promising.

Iterative decimal multiplication using binary arithmetic

Abstract: The IEEE-754 2008 standard for floating point arithmetic has definitely dictated the importance of decimal arithmetic. Human-centric applications, like financial and commercial, depend on decimal arithmetic since the results must match exactly those obtained by human calculations. A few hardware approaches have been proposed for decimal arithmetic, including addition, subtraction, multiplication and division. Parallel implementations for these operations are very expensive in terms of occupied resources and therefore implementations based on iterative algorithms are good alternatives. In this paper, we propose an iterative decimal multiplier for FPGA that uses binary arithmetic. The circuits were implemented in a Xilinx Virtex 4 FPGA. The results indicate that the proposed iterative multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.

The MPRACE framework: An open source stack for communication with custom FPGA-based accelerators

Abstract: We present an open source stack for the development of custom FPGA boards, primarily but not limited to PCI Express interconnects. Supporting current Linux distributions, the stack consists of a PCI driver, an IP core for a DMA engine, a hardware abstraction library for IO operations, and a buffer management library for efficient handling of data transfers between an application and a FPGA design. The stack has been validated in diverse hardware and software platforms and provides several building blocks that facilitate the use of accelerators in applications. The DMA Engine IP provides high performance data transfers in PCIe 4-lane boards with Xilinx PCIe cores, with 380 MB/s read and 700 MB/s write maximum measured performance. The buffer management library allows the utilization of 80–95% of this bandwidth with reduced resource consumption and minimal effort.

Power estimations vs. power measurements in Cyclone III devices

Abstract: This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers implemented in LUTs and in embedded blocks both with or without pipelining stages. Three type of results are presented: first, the error between power measurements and power estimations; second, the power savings by using pipeline stages, and third, the quantification of power savings by using embedded blocks.

FPGA implementation of an ultra-high speed ADC interface

Abstract: Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

FPGA implementation of a chaotic oscillator using RK4 method

Abstract: The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices.

Hardware Particle Swarm Optimization with passive congregation for embedded applications

Abstract: Achieving high performance optimization algorithms for embedded applications can be very challenging, particularly when several requirements such as high accuracy computations, short elapsed time, area cost, low power consumption and portability must be accomplished. This paper proposes a hardware implementation of the Particle Swarm Optimization algorithm with passive congregation (HPPSOpc), which was developed using several floating-point arithmetic libraries. The passive congregation is a biological behavior which allows the swarm to preserve its integrity, balancing between global and local search. The HPPSOpc architecture was implemented on a Virtex5 FPGA device and validated using two multimodal benchmark problems. Synthesis, simulation and execution time results demonstrates that the passive congregation approach is a low cost solution for solving embedded optimization problems with a high performance.

An unified approach for convolution-based image filtering on reconfigurable systems

Abstract: Currently the market and the academic community have required applications of image and video processing with several real-time constraints. In order to seek an alternative design that allows the rapid development of real time image processing systems this paper proposes an unified hardware architecture for some image filtering algorithms in space domain, such as windowing-based operations, which are implemented on FPGAs (Field Programmable Gate Arrays). For achieving this, six different filters have been implemented in a parallel approach, separating them in simple hardware structures, allowing the algorithms to explore their parallel capabilities by using a simple systolic architecture. In this system all implemented algorithms run in parallel allowing the user to select a defined output for depicting it in a display. Both image processing and synthesis results have demonstrated the feasibility of FPGAs for implementing the proposed filtering algorithms in a full parallel approach.

An extensible code generation framework for heterogeneous architectures based on IP-XACT

Abstract: In this paper, we examine the problem of abstracting the design process for heterogeneous CPU/FPGA systems from the perspective of a group of engineers designing telecommunications systems, and propose a design flow that addresses the constraints imposed in an industrial context whilst striving for maximal compatibility with existing tools and research projects. We thus present a modular and extensible flow based around the IP-XACT standard, which is gaining support in industry, and link this to a front-end built on the semantics of dataflow process networks and a template-based code generation back-end.

A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor

Abstract: This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and subtraction on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP numbers and is based on a fully pipelined circuit. The design presents a novel hardware for pre-signal generation stage and an enhanced version of previously published leading zero stage. The design can operate at a frequency of 200 MHZ on a Virtex-5 with a latency of 8 cycles. The presented DFP adder/subtractor supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To our knowledge, this is the first hardware FPGA design for adding and subtracting IEEE 754-2008 using decimal64 encoding.

Design of a FPGA based position PI servo controller for a DC motor with dry friction

Abstract: In this paper we present the design, implementation and experimental validation of a FPGA based position servo controller for a DC motor with dry friction. VHDL and block diagram modules for trajectory generation, encoder signal decoding, PI controller and PWM control signal generation are described. The control system is implemented in the DE3 board of Terasic Technologies Inc using Quartus II environment of Altera Corporation. Servo system simulation was made using Simulink. The analytical non linear model for the anti-windup saturation on the integral control action, saturation on the actuator and dry friction is validated through experiments and simulations.

Fast parallel audio fingerprinting implementation in reconfigurable hardware and GPUs

Abstract: One of the main challenges that Music Information Retrieval (MIR) faces is performance. This paper presents an algorithm based on fingerprinting techniques implemented in a low-cost embedded reconfigurable platform. This fast algorithm is even faster when implemented in parallel for a GPU platform. The hit rate of the implementations is practically 100% and the response time is two times faster than the response time of a top class PC, which means MIR times of up to 65 audio tracks in real time.

A novel method for secure intellectual property deployment in embedded systems

Abstract: The configuration data sequence of a Field Programmable Gate Array (FPGA) is an Intellectual Property (IP) of the original designer. With the increase in deployment of FPGAs in modern embedded systems, the IP protection of FPGA has become a necessary requirement for many IP vendors. There have been already many proposals to overcome this problem using symmetric encryption techniques but these methods need a cryptographic key to be stored in a non-volatile memory located on FPGA or in a battery-backed RAM as done in some of the current FPGAs. The expenses with the proposed methods are, occupation of larger area on FPGA in the former case and limited lifetime of the device in the latter. In contrast, we propose a novel method which combines the Dynamic Partial Reconfiguration (Dynamic PR) feature of an SRAM-based FPGA with the Public Key Cryptography (PKC) to protect the FPGA configuration files without the need of fixed key storage on FPGA or external to FPGA. The proposed method, is secure against the known attacks such as the Man-In-The-Middle (MITM) attack and replay attack. Therefore, the method can be used for secure deploying of IPs from local and remote vendors. Also, using this novel method not only high-end FPGAs but also low-end FPGAs with PR capabilities are secured.

FPGA-based random pulse generator for emulation of a neutron detector system in a nuclear reactor

Abstract: In this work an FPGA-based emulator of a pulse-mode neutron detector system is presented. The equipment emulates the digital output of a discriminator circuit and permits the generation of pulse trains ranging from 0.5 pulse/s to 1 Mpulse/s. The emulation is based on a synchronous version of a Poisson process generator using Bernoulli trials. The emulator is controlled via a serial connection to a computer and both the pulse-width and the mean pulse-rate can be dynamically updated; thus, making possible the emulation of a detector evolution when a nuclear reactor is in its start-up/shutting-down phase. To also consider the dead-time effects present in pulse-mode detector systems, the equipment implements the paralyzable and nonparalyzable dead-time models. The emulator also incorporates a data-logger module to record interarrival-time values of the generated pulse train. This last feature can be used to calibrate a rate-meter equipment and to verify the statistics of the emulator's output signal.

An Euler solver accelerator in FPGA for computational fluid dynamics applications

Abstract: This paper addresses the problem of accelerating Computational Fluid Dynamics (CFD) applications, utilized by aeronautical engineers to create more efficient and aerodynamic designs. CFD applications require intensive floating point calculations, so they are usually executed on High-Performance Computing (HPC) systems. Here, we study the HW implementation of a cell-vertex finite volume algorithm to solve Euler equations, using the XtremeData XD2000i in-socket FPGA accelerator. Taking advantage of high-level language synthesis tools together with optimized low level components, a HW-accelerated implementation that achieved speedups up to 13.25x could be created in a short time.

A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems

Abstract: This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.

Custom FPGA-based micro-architecture for streaming computing

Abstract: This paper describes a micro-architecture for a custom programmable FPGA-based processor, with direct support for streaming and vector computations relying on custom cache memory storage. The processor combines a custom data-path with several parallel data ports for accessing operands in streaming mode thus efficiently supporting nested looping constructs found in high-level languages while mitigating the impact on external memory bandwidth. The architecture leverages the strided access patterns of streaming data access using a microcoded sequencer with multi-dimensional nested looping capability. We present synthesis results for the main components of the architecture on a Xilinx's Virtex-4 FPGA device. The results reveal the architecture to be extremely flexible and consume few FPGA resources.

Architecture driven memory allocation for FPGA based real-time video processing systems

Abstract: In this paper, we present an approach that uses information about the FPGA architecture to achieve optimized allocation of embedded memory in real-time video processing system. A cost function defined in terms of required memory sizes, available block- and distributed-RAM resources is used to motivate the allocation decision. This work is a high-level exploration that generates VHDL RTL modules and synthesis constraint files to specify memory allocation. Results show that the proposed approach achieves appreciable reduction in block RAM usage over previous logic to memory mapping approach at negligible increase in logic usage.

FPGA and ASIC convergence

Abstract: The growing demands on multimedia applications and high-speed high-quality telecommunication systems with real-time constrains oriented to portable, low power consumption, devices, have being driven technologies development, methodologies and design flows of embedded systems during the last years. Through the analysis of design methodologies and strategies facing multi-core, reconfigurability and power consumption challenges, this educational survey will follow that evolution approaching ASIC and FPGA architectures on the embedded systems arena.

A dynamic buffer resize technique for networks-on-chip on FPGA

Abstract: Networks-on-chip have a relative area and delay overhead compared to buses. These can be improved in application specific systems where heterogeneous communication infrastructures provide high bandwidth in a localized fashion and reduce underutilized resources. However, for general purpose architectures, design time techniques are not efficient. One approach for improving area and/or performance of NoCs for general purpose systems is to consider dynamic adaptation of the resources at runtime. In this paper, we analyze the buffer resize approaches applied to FPGA and propose a buffer resize technique. The results show that the technique improves the area and the performance of the architecture on FPGA but is less efficient than ASIC implementations.

A high data rate BPSK receiver implementation in FPGA for high dynamics applications

Abstract: In this paper we present the implementation of a FPGA based high data rate BPSK receiver specifically designed to withstand the high dynamics of airborne vehicles (i.e. aircraft, sounding rockets, satellites, etc.). The carrier recovery is implemented through a Costas loop, and a Gardner detector is used for the timing recovery. This architecture was chosen because it provides almost independent carrier and bit synchronization. Loop filters were designed through analog to discrete-time conversion. A theoretical analysis of the design, simulation and its implementation is presented.

Experiences applying framework-based functional verification to a design for programmable logic

Abstract: This paper presents experiences in applying modern functional verification to a configurable decimal floating point Adder / Subtractor core targeted to programmable logic. Despite its huge input space, a number of hard-to-verify corner cases are identified. Two different verification frameworks were applied in order to develop testbenches: OVM and Truss. These tesbenches were built to be independent of the ALU operand representation and IEEE754-2008 specific modules were also implemented. Verification results, the experience itself, and a comparative study of the alternatives was made and summarized for designers and verification engineers.

Synthesis of robust controllers for GALS_FPGA from multi-burst graph specification

Abstract: Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used to implement circuits in FPGAs (Field Programmable Gate Array). Although these devices have the benefits of low-cost and short development time, there's a major drawback which is implementing Asynchronous Interfaces (AI) in FPGA devices. There's a typical AI design style which is based on asynchronous controllers that provides communication between modules (called ports), but Port controllers are subject to essential-hazard when implemented FPGAs. This paper proposes a method based on direct mapping to implement these ports. It begins with an MBG (multi-burst graph) specification and makes use of the essential signal concept to check if the resulting circuit is hazard-free, or to point potential essential-hazard problems in the circuit. By satisfying the essential signal condition, this method is capable of providing robust ports, i.e. essential-hazard-free.

Known-blocking. Synchronization method for reliable processor using TMR & DPR in SRAM FPGAs

Abstract: The need of critical applications has derived in the development of several safety techniques that aim to guarantee system operability. The vast majority of these systems own a microprocessor to control its functionality. Thus, system reliability largely depends on the proper function of the microprocessor. In the special case of SRAM FPGAs, Triple Modular Redundancy (TMR) combined with Dynamic Partial Reconfiguration (DPR) allows the development of coarse grain modularity architectures where the redundant module is a soft-core microprocessor or a more complex logical unit based in a processor. However, its main lack is a suitable synchronization method for the faulty module once it is reconfigured. This paper shows the trends on synchronization methods for systems that make use of TMR and DPR and proposes a new synchronization method based on a non blocking scheme.

High speed acquisition and storage platform for SDR applications development

Abstract: In this work we present the design of an FPGA based platform for acquiring and storing signals for SDR applications. The system comprises an embedded RISC processor, an A/D converter, RAM memory chips and a DMA controller core. This last component was designed from scratch to meet the high data rate and bulk requirements.