Symposium on VLSI Technology 

About: Symposium on VLSI Technology is an academic conference. The conference publishes majorly in the area(s): CMOS & MOSFET. Over the lifetime, 3259 publications have been published by the conference receiving 63272 citations.

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Abstract: We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

Abstract: Vertical NAND flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

Abstract: A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.

Stable SRAM cell design for the 32 nm node and beyond

Abstract: SRAM cell stability will be a primary concern for future technologies due to variability and decreasing power supply voltages. 6T-SRAM can be optimized for stability by choosing the cell layout, device threshold voltages, and the /spl beta/ ratio. 8T-SRAM, however, provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling. We demonstrate the smallest 6T (0.124/spl mu/m/sup 2/ half-cell) and full 8T (0.1998/spl mu/m/sup 2/) cells to date.

Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices

Abstract: We propose pipe-shaped bit cost scalable (P-BiCS) flash memory which consists of pipe-shaped NAND strings folded like a u-shape instead of the straight-shape. P-BiCS flash technology achieves a highly reliable memory film of which the program and erase (P/E) operation is managed by Fowler-Nordheim (FN) tunneling, that is originated by the strong curvature effect of its small pipe radius, a low resistance source line by the layered metal wirings and a tightly controlled diffusion profile for the select-gate (SG) transistor due to low thermal budget. The effective 1-bit cell area of 0.00082 mum2 and its functionality are successfully demonstrated using the 32 Gbit test chip with the 3-dimensionally 16 stacked layers and the multi-level-cell (MLC) operation by 60 nm P-BiCS flash technology.