Very Large Scale Integration of System-on-Chip
About: Very Large Scale Integration of System-on-Chip is an academic conference. The conference publishes majorly in the area(s): Fault coverage & Fault (power engineering). Over the lifetime, 32 publication(s) have been published by the conference receiving 207 citation(s).
Topics: Fault coverage, Fault (power engineering), Reconfigurable computing, Logic synthesis, Automatic test pattern generation
01 Jan 2003
01 Oct 2006
TL;DR: This paper presents an organic computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques.
Abstract: The evolution of CMOS technologies leads to integrated circuits with ever smaller device sizes, lower supply voltage, higher clock frequency and more process variability. Intermittent faults effecting logic and timing are becoming a major challenge for future integrated circuit designs. This paper presents an Organic Computing inspired SoC architecture which applies self-organization and self-calibration concepts to build reliable SoCs with lower overheads and a broader fault coverage than classical fault-tolerance techniques. We demonstrate the feasibility of this approach by example on the processing pipeline of a public-domain RISC CPU core.
16 Oct 2006
TL;DR: Results show that the proposed structural-based power-aware X-filling technique provides the best tradeoff between peak power reduction and increase of test sequence length.
Abstract: Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits with the proposed structural-based power-aware X-filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length.
01 Jan 2006
TL;DR: A qualified decision can be done between fine-grain FPGAs of different sizes and different dynamic reconfiguration frequencies, e.g. using smaller and more cost- as well as power-efficient FPGA by temporarily outsourcing suitable functionalities.
01 Oct 2009
TL;DR: A new on-chip monitoring system, allowing failure anticipation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops, made of special structures situated near the flip- flops, coupled with a specific detection window generator, embedded within the clock-tree.
Abstract: PVT monitors are mandatory to use tunable knobs designed to compensate the variability effects. This paper describes a new on-chip monitoring system, allowing failure anticipation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of special structures situated near the flip-flops, coupled with a specific detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area fine-grain system, easily insertable in a standard CAD flow.
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