Workshop On Computer Architecture Education 

Abstract: We have built an interactive, visual pipeline simulator, called dlxview, for the DLX instruction set and pipeline described in Computer Architecture A Quantitative Approach by Hennessy and Patterson [1]. This software provides animated versions of key figures and tables from the text and allows the user to readily follow details of pipeline activity as a code is simulated, to vary pipeline implementation, and to compare performance across different pipeline designs.The software package requires a system running Unix and X11, with Tcl/Tk installed, and using the GNU gcc compiler is recommended. A 256 color display with 1024x768 pixels is best for display, due to the detailed diagrams of the DLX pipeline. The software has been designed to run on a variety of platforms and has been tested on Solaris 2.3, SunOS 4.1.1, HP-UX 9.0, DEC OSF/1 4.0, and Linux kernel 1.2.1. DLXview is available at http://yara.ecn.purdue.edu/~teamaaa/dlxview/

Abstract: We have developed ESCAPE, an easy-to-use, highly interactive portable PC-based simulation environment aimed at the support of computer architecture education. The environment can simulate both a microprogrammed architecture and a pipelined architecture with single pipeline. Both architectures are custom-made, with a certain amount of configurability. Other tools, such as a memory monitor, assembler/disassembler and analysis tools, such as on-the-fly generation of pipeline activity and usage diagrams, are integrated with the environment.Based upon our limited experience with the material so far, we can state that the results are excellent. Students invariantly respond very positively, and the evaluations indicate a far deeper understanding than was previously attainable by using only the traditional textbook-and-paper-problems approach.

Abstract: The paper presents an environment for teaching elements of a computer system memory hierarchy. It is made up of a hierarchical memory system, a reference manual, a software package and a set of laboratory experiments. The hierarchical memory system is devised to cover the virtual memory and translation lookaside buffer, the cache memory, and the main memory. The reference manual provides all implementation details with the appropriate circuits drawings and detailed descriptions. For the devised hierarchical memory system a software package, which includes the graphical simulator with the accompanying tools, is developed. They allow one to carry out the simulation down to the register transfer level by executing a set of laboratory experiments.

Abstract: Field programmable gate arrays are an ideal substrate for computer architecture project courses. FPGA-based processor development offers some learning opportunities that pure simulation approaches cannot rival. This paper first introduces the XSOC Project, a free kit that includes the xr16 RISC CPU core, system-on-a-chip infrastructure, peripheral cores, C compiler, and simulator. Such kits have numerous applications in a first architecture course. It then suggests that FPGA-based processors can also be applied to the study of advanced architecture topics including memory systems, multithreading, LIWs, chip multiprocessors, and architectural support for programming languages and networking.