Showing papers presented at "Workshop On Computer Architecture Education in 2007"

A pedagogically targeted logic design and simulation tool

Abstract: JLS is a GUI-based digital logic simulation tool specifically designed for use in a wide range of digital logic and computer organization courses. It is comparable in features and functionality to commercial products, but includes many student and instructor-friendly aspects not found in those products such as state-machine and truth table editors, extensive error checking, and multiple simulation-result views. Students quickly become proficient in its use, enabling them to concentrate on circuit design and debugging issues. The circuit drawing interface is convenient enough to allow instructors to use it for classroom presentations, and circuits can be modified and tested so quickly that it promotes exploring alternatives not prepared for in advance. Its non-interractive (batch) execution capability, with parameter settings, configuration files and textual output simplifies the grading of large numbers of student projects.

An experimental laboratory environment for teaching embedded hardware systems

Abstract: This paper describes Marquette University's efforts to build an experimental embedded systems laboratory for hands-on projects in an introductory hardware systems course Our prototype laboratory is now serving as the basis for a coherent sequence of class projects threaded throughout subsequent courses in operating systems, networking, and embedded systems, among others We describe the major components of our laboratory environment, how it is used in our hardware systems course, and how this has contributed to significant improvements in other core courses in our curriculum

Pedagogic value in understanding computer architecture of implementing the marie computer from null and lobur in the logic emulation software, multimedia logic

Abstract: In our computer architecture course, we ask students to design an instruction set for an eight- or sixteen-bit computer and then implement that design in an emulated computer using a logic emulation package. In Winter semester 2006 a team of three students decided to design and implement the "Marie" computer instruction set described in the book by Null and Lobur[2]. The project proved to be highly motivational for this team, and they produced an excellent result. This paper describes that design process, the resulting computer, and learning from the project.

VLIW-DLX simulator for educational purposes

Abstract: VLIW-DLX is graphical simulator of simple VLIW processor. It is targeted to be used in undergraduate computer architecture courses. VLIW-DLX uses similar GUI to well-known WinDLX simulator and its ISA uses scalar DLX instructions as the building blocks. Simulator is implemented in Java and allows future modifications of the architecture including instruction set expansion. Paper discusses choices made in developing VLIW-DLX and its intended educational use.

An integrated approach to teaching computer systems architecture

Abstract: At Georgia Tech, since the Fall of 1999, we have been teaching a first course in systems that represents a radical departure from the usual stovepipe model of teaching computer architecture and operating systems. By making this course a required one for CS majors in their sophomore year, we have accomplished several goals the most important of which is the opportunity for students to pursue deeper exposure to systems in their junior and senior years, through additional courses and research, if they so choose. The pedagogical style embodied in this course fosters a good understanding of the symbiotic relationship between hardware and software for the students early on in their undergraduate experience.

Understanding cache hierarchy interactions with a program-driven simulator

Abstract: The increasing importance of the cache hierarchy in almost all digital systems governed by a microprocessor is demanding an appropriate set of tools to teach the interactions between caches. Students in computer organization/architecture courses face the problem of understanding how caches interact in a hierarchical organization. As caches grow in size and complexity, designing a tool to explore the different parameter interactions becomes challenging. Also, focusing only on the significant information (accessed lines and events) at different cache levels is required.In this paper we present SpimVista, a tool developed on top of PC-Spim simulator, that simulates any MIPS code on a system with different cache hierarchy configurations. Each cache memory can be configured independently.SpimVista is aimed at being used by undergraduate students, and the graphical interface has been designed addressed to ease the learning process. In particular, the tool offers an intuitive and easy interface that allows the student to focus on particular and interesting events as the program instructions are executed step-by-step. Also, students can perform interesting exercises where both the code and the impact of cache organization parameters on performance are analyzed globally.

Teaching computer organization/architecture by building a computer

Abstract: This paper describes a series of exercises and assignments suggested for an introductory computer organization or computer architecture course. The primary objective of these exercises is to engage a class of students by introducing the practical, hands-on application of assembling a computer by selecting or purchasing individual components. While the ideal implementation involves the purchasing and assembling of components, various alternatives will be presented that do not require any additional funds to be secured.

ChipDesign: from theory to real world

Abstract: This paper presents our experiences and describes the details of a project-oriented ASIC design course held at Leibniz University Hannover. Our approach for this curriculum is to bring a real project (AVR instruction compatible microcontroller) into the classroom and introduce a professional standard cell based chip-design to the students. Moreover, the students are responsible for the organization of the overall project, improving their social skills and the ability to manage conflicts. The feedback shows that this approach is implementable and fulfills the required needs for both, industry and university curriculum.

Animations of important concepts in parallel computer architecture

Abstract: Resources for teaching parallel computer architecture--specifically, cache coherence and memory consistency--are increasing in importance. Through instructor-created templates, followed by peer-reviewed student work, we have produced a set of animations that can be used for classroom presentation or self-study. These animations cover bus-based coherence protocols, such as MSI, MOESI, and Dragon; and network-based protocols, such as the full bit-vector scheme and a simplified version of SCI. Some animations illustrate the operation of a particular protocol, while others compare protocols against each other. Other animations cover memory-consistency models, such as sequential consistency, processor consistency, weak ordering, and release consistency.

From classroom to research: providing different services for computer architecture education

Abstract: T&D-Bench (Teaching and Design Workbench) is now a mature framework for processor modeling and simulation. The framework's processor models have been employed by students to execute practical exercises in Computer Architecture (CA) courses and, by the instructors, to illustrate CA concepts in classroom. The framework itself has been employed by seniors and researchers to make the design space exploration of embedded processors, which is accomplished by modeling new processors or by extensions to the existing processor models. The results of the research activities, incorporated to the processor models, may then be employed in classroom, producing a virtuous circle. This work describes all the services developed for T&D-Bench along the last years. For example, a practical use in research to model an architectural feature that reduces energy consumption, as well as a comparison with a well-established Architecture Description Language are presented.

A proposal to introduce power and energy notions in computer architecture laboratories

Abstract: Power has emerged as a major concern in the microprocessor industry. From embedded to high-performance processors, all designs employ several power optimizations at the circuit and the architectural levels.While introductory computer architecture books and courses are starting to cover power concepts, proposals to offer students a practical experience with power issues are still scarce. To do so, we advocate the inclusion of energy and power concepts in computer architecture courses by means of laboratory experiments. These experiments build upon concepts presented in preceding physics and/or electronics courses.This paper outlines our experience with the development of such hardware-based energy laboratories. We propose experiments on a simple, yet powerful hardware-software platform capable of live energy measurements in a desktop computer processor. The proposed laboratory setup can help to teach students the basics of power-aware computer architectures. The performed experiments demonstrate the viability of our approach. For example, our experiments show that students can deduce the dynamic and static power dissipation of the Intel Pentium 4. Information that is not documented in the processor's datasheet.

Industry perspective on chip multi-threading, bridging the gap with academia using OpenSPARC

Abstract: Chip Multi-Threading is the new wave that is sweeping this decade. It is no more a theoretical discussion topic but one where revolutionary products with CMT will permeate every aspect of computing infrastructure. So, how does Academia innovate on this new frontier? Sun Microsystems has contributed to the open-source community a large state-of-the-art design called the, OpenSPARC T1. This new open source version of the UltraSPARC T1 design is a 64 bit, 32 threaded processor design available at no charge. For the first time in history, developers gain access to the chip multi-threading (CMT) technology unique to the UltraSPARC T1 processor, which is released under the GNU General Public License (GPL). The specifications, verilog RTL, verification environment, diagnostic test suite, SPARC Architecture Model, instruction accurate simulator, OBP, hypervisor and Solaris OS image are all made available.In this presentation we will discuss what Sun Microsystems is doing to bring a commercial CMT architecture and design into the classroom, "Bridging the gap" between industry and academia.