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Conference

Workshop On Computer Architecture Education 

About: Workshop On Computer Architecture Education is an academic conference. The conference publishes majorly in the area(s): Cache & Instruction set. Over the lifetime, 107 publications have been published by the conference receiving 531 citations.

Papers published on a yearly basis

Papers
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Proceedings ArticleDOI
01 Jan 1997
TL;DR: An interactive, visual pipeline simulator, called dlxview, for the DLX instruction set and pipeline described in Computer Architecture A Quantitative Approach, which provides animated versions of key figures and tables from the text and allows the user to readily follow details of pipeline activity as a code is simulated.
Abstract: We have built an interactive, visual pipeline simulator, called dlxview, for the DLX instruction set and pipeline described in Computer Architecture A Quantitative Approach by Hennessy and Patterson [1]. This software provides animated versions of key figures and tables from the text and allows the user to readily follow details of pipeline activity as a code is simulated, to vary pipeline implementation, and to compare performance across different pipeline designs.The software package requires a system running Unix and X11, with Tcl/Tk installed, and using the GNU gcc compiler is recommended. A 256 color display with 1024x768 pixels is best for display, due to the detailed diagrams of the DLX pipeline. The software has been designed to run on a variety of platforms and has been tested on Solaris 2.3, SunOS 4.1.1, HP-UX 9.0, DEC OSF/1 4.0, and Linux kernel 1.2.1. DLXview is available at http://yara.ecn.purdue.edu/~teamaaa/dlxview/

22 citations

Proceedings ArticleDOI
01 Jun 1998
TL;DR: In this paper, ESCAPE, an easy-to-use, highly interactive portable PC-based simulation environment aimed at the support of computer architecture education, is presented, which can simulate both a microprogrammed architecture and a pipelined architecture with a single pipeline.
Abstract: We have developed ESCAPE, an easy-to-use, highly interactive portable PC-based simulation environment aimed at the support of computer architecture education. The environment can simulate both a microprogrammed architecture and a pipelined architecture with single pipeline. Both architectures are custom-made, with a certain amount of configurability. Other tools, such as a memory monitor, assembler/disassembler and analysis tools, such as on-the-fly generation of pipeline activity and usage diagrams, are integrated with the environment.Based upon our limited experience with the material so far, we can state that the results are excellent. Students invariantly respond very positively, and the evaluations indicate a far deeper understanding than was previously attainable by using only the traditional textbook-and-paper-problems approach.

21 citations

Proceedings ArticleDOI
01 Jun 2000
TL;DR: An interactive animation tool, SATSim, which conveys superscalar architecture concepts, which allows students to interactively change hardware configuration parameters and to observe their effects visually in a more accessible manner than is currently possible with existing simulators or with traditional static media.
Abstract: This paper describes an interactive animation tool, SATSim, which conveys superscalar architecture concepts. It has been used in an advanced undergraduate computer architecture course to visualize the complicated behavioral patterns of superscalar architectures, such as out-of-order execution, in-order commitment, and the impact of branch mispredictions and cache misses. SATSim allows students to interactively change hardware configuration parameters and to observe their effects visually in a more accessible manner than is currently possible with existing simulators or with traditional static media.

21 citations

Proceedings ArticleDOI
01 Jun 1998
TL;DR: An environment for teaching elements of a computer system memory hierarchy is presented, made up of a hierarchical memory system, a reference manual, a software package and a set of laboratory experiments.
Abstract: The paper presents an environment for teaching elements of a computer system memory hierarchy. It is made up of a hierarchical memory system, a reference manual, a software package and a set of laboratory experiments. The hierarchical memory system is devised to cover the virtual memory and translation lookaside buffer, the cache memory, and the main memory. The reference manual provides all implementation details with the appropriate circuits drawings and detailed descriptions. For the devised hierarchical memory system a software package, which includes the graphical simulator with the accompanying tools, is developed. They allow one to carry out the simulation down to the register transfer level by executing a set of laboratory experiments.

20 citations

Performance
Metrics
No. of papers from the Conference in previous years
YearPapers
20199
20173
20159
200712
200017
19994