Showing papers by "Agilent Technologies published in 1993"

Network analysis method

Abstract: A network analysis method for use in relation to a network having a plurality of entities, each with associated traffic, involves an analysis task comprising the steps of monitoring the network to collect data on entity traffic for a period of network operation, analyzing this data in respect of an entity operational characteristic by which the entities may be ordered into a ranking, forming an end set of at least one entity at one end of said ranking, and storing the identity of the or each entity making up that end set. The analysis task is carried out for a succession of N periods, where N is an integer greater than unity, to form an extended historical record of entities in the end sets for those N periods; the analysis task is then carried out for a further period and the entities in the resulting newly-created end set are compared with the entities in the extended historical record, to identify any entity (an `unusually-behaved` entity) that is in the newly-created end set but not also in the historical record.

Surface emitting second harmonic generating device

Abstract: A surface emitting second harmonic generating device capable of generating a second harmonic at room temperatures with high efficiency and output power, and which has a small size, low energy consumption and a low manufacturing cost. A second harmonic is efficiently generated when the direction of the semiconductor crystals within a cavity makes an angle of 5° or more with respect to the direction of the light rays (particularly when one of the , and directions approximately matches the direction of the light rays). Further, if a superlattice second harmonic generating layer composed of a III-V or II-VI compound semiconductor is provided between the output end reflector and the spacer layer, the second harmonic may be generated with even greater efficiency. In addition, the spacer layer may be formed by a superlattice, as may the active layer and the spacer layers. A second harmonic may also be efficiently generated by utilizing the spacer layer and the active layer as phase-matching layers.

Sealed parts leak testing method and apparatus for helium spectrometer leak detection

Abstract: Small, hermetically sealed pans are leak tested after subjecting the finished device to an environment of trace gas such as helium. During the testing process the pans may lose their helium charge by rapid escape due to massive gross leaks. These cases demand pre-helium mass spectrometer leak detector gross leak testing procedure. The non-helium expansion technique, used in conjunction with a helium mass spectrometer leak detector, provides a reliable and automatic gross and fine leak testing of the pans by a single apparatus. The test pan is placed in a sealed test fixture, and a valve between the test fixture and an expansion chamber is opened. The pressure in the expansion chamber is measured after the valve is opened. When the measured pressure is less than a reference pressure, a leaking test pan is indicated. When a sealed test pan is indicated, a helium mass spectrometer leak test is performed to determine the presence of fine leaks in the test part.

Database management system embedded in an operating system command

Abstract: A database system embedded in an operating system command. The system is invoked by operating system commands and uses no system resources except when performing a command. Searching is performed by binary search on a sorted file and sequential search on an unsorted file. New and changed records are appended to the unsorted file and the files are merged whenever the unsorted file becomes too long.

Low leakage diode switches for a tester circuit for integrated circuits

Abstract: Pin electronics for an IC tester are built as an integrated circuit for testing the electrical operation of a device under test (DUT) by applying a test voltage to each of the pins on the DUT and measuring each resulting current. The tester uses diode switches instead of discrete relays to switch between measurement ranges. Leakage current, on the order of nanoamperes from a switch that is open or disabled, is dramatically reduced by reverse biasing the diodes in each diode switch about the switch's diode bridge output node by an equal amount so that the summed current at the output node is almost zero.

Precision integrated resistors

Abstract: Pin electronics for an IC tester are built as an integrated circuit for characterizing the electrical operation of a device under test (DUT) by applying a test voltage to each of the pins on the DUT and measuring each resulting current. Typically, an IC tester selects one of several measure resistors, applies a stimulus to a pin of the DUT using an input driver, and measures the current response of the DUT through the related measure resistor. Each measure resistor corresponds to a specific current range and measurement accuracy is proportional to the precision of the selected resistor. Each measure resistor is a series of precision integrated resistors having a very low leakage current. This provides for current measurements of high sensitivity.

Transdermal cell test matter volume-adjustment device

Abstract: In a transdermal cell, a matter volume-adjustment male device includes the lower opening end of the through-space structure having inner wall female threads mateable with first male threads of a screwable matter volume-adjustment male member alternately adjustable upwardly and downwardly between opposite upper and lower female threads-termination points. The screwable matter volume-adjustment member has opposite first upper and lower male threads-termination points, and the inner wall female threads are further concurrently mateable with a bottom closure member having second male threads having opposite second upper and lower male threads-termination points. There is a first annular sealing ring sealably mounted in an annular groove around the screwable volume-adjustment male member between the first upper and lower threads-termination points positioned between the inner wall female threads and the first male threads, and there being a second annular sealing ring sealably mounted the second male threads at a location below the second upper termination point.

Multi-layer fabrication in integrated circuit systems

Abstract: A method for fabricating layers permits the accurate removal of surface material in a multi-layer multi-chip carrier. An intermediate layer of solid vias is deposited over a circuit layer attached to a substrate. The layer can be filled with a dielectric material. The substrate is attached to a substrate holder such that the intermediate layer is exposed, and the substrate holder is placed onto a rotating platen polisher with the intermediate layer facing the platen surface. Tooling presses the intermediate layer against the rotating polishing platen, allowing the substrate holder and substrate to rotate with three degrees of angular freedom, letting the substrate and intermediate layer self-align to the polishing platen in order to uniformly remove material from the intermediate layer surface. A second circuit layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure of circuit layers separated by uniformly thick dielectric and via layers. As an alternative method, substrate attached to a substrate holder is placed against the platen surface of a shaking polisher, allowing the substrate and substrate holder to self-align to the polishing platen. In a third embodiment, where metal irregularities exist along the intermediate layer surface, wiping the surface evenly with cloth soaked in an appropriate etchant can uniformly remove the unwanted metal irregularities.

Method of fabrication of adjacent coplanar semiconductor devices

Abstract: A method for processing coplanar semiconductor devices of different types as provided. The method includes the steps of: forming a first layer for formation of a first device region on a substrate, forming an epitaxial semiconductor lift-off layer above the first device region, removing a portion of the first device region to open areas for the formation of the second device region, depositing epitaxially a second device region, and removing the liftoff layer to leave the first and second device regions remaining on the substrate.

Push column and chromatography apparatus

Abstract: An apparatus for chromatography of DNA, RNA, proteins and other molecules includes the use of a column adapted to hold a chromatography material and a sample to be filtered. A pneumatic pressure differential is applied across the column and the sample is urged through the chromatography material. A selected portion of the sample may then be collected.

Improved single and multistage stage FIFO designs for data transfer synchronizers

Abstract: An improved multi-stage synchronizer. The inventive synchronizer includes a first memory for storing data, a second memory means connected to the output of said first memory means for storing data, and a third memory for storing data connected to the output of said second memory means. The second memory includes a plurality of multi-stage first-in, first-out memory devices. In a particular embodiment, the first and third memories are implemented with synchronous single stage first-in, first-out memories. In a preferred embodiment, the first-in, first-out memories are designed to allow data to be read and written during a single clock cycle after the memory is full. This is achieved by adding an external read signal to the 'not full' signal generated by the device. The provision of single stage FIFO memories on either side of a multi-stage FIFO memory allows for lower set up time and output delay at higher operational speeds.

Method for selective collisional dissociation using border effect excitation with prior cooling time control

Abstract: A variable cooling time is imposed on ions in a quadrupole ion trap prior to excitation through border effect operation. Continuous variation of the cooling time brings about continuous variation of the selected ion internal energy when subjected to the boundary effect such that the boundary effect competes more favorably with ion loss in the trap, and fragmentation reaction channels having successively greater energies of activation can be accessed preferentially.