Institution
Amkor Technology
Company•Tempe, Arizona, United States•
About: Amkor Technology is a company organization based out in Tempe, Arizona, United States. It is known for research contribution in the topics: Semiconductor package & Die (integrated circuit). The organization has 1069 authors who have published 1106 publications receiving 26778 citations. The organization is also known as: Amkor & Amkor Technology, Inc..
Topics: Semiconductor package, Die (integrated circuit), Substrate (printing), Flip chip, Quad Flat No-leads package
Papers published on a yearly basis
Papers
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01 Jun 2004TL;DR: In this paper, the authors describe in detail the life prediction models for SnAgCu solder joints, which are based on published constitutive equations for this alloy and thermal cycle fatigue data on actual components.
Abstract: Pb free solder is fast becoming a reality in electronic manufacturing due to marketing and legislative pressures. The industry has pretty much concluded that various versions of SnAgCu solder alloy offer the best alternative for eutectic Sn/Pb solder currently in use. With the current trend of cheaper, faster, and better electronic equipment, it has become increasingly important to evaluate the package and system performance very early in the design cycle using simulation tools. This requires life prediction models for new solder alloy systems so that the package-to-board interconnect reliability can be predicted for various environmental and field conditions. This paper describes in detail the life prediction models for SnAgCu solder joints. The models are based on published constitutive equations for this alloy and thermal cycle fatigue data on actual components. The approach uses advanced finite element modeling and analysis techniques and is based on mechanics of deformation. Both accumulated creep strain and creep strain energy density based models are developed. The model has been correlated with a number of data points and predicts life within 25% in most cases. The framework of modeling and prediction methodology described here is fully compatible with the framework used for SnPb solder previously.
353 citations
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05 May 2000TL;DR: In this paper, a semiconductor package and a method for fabricating the same is presented, which includes a circuit board composed of a resin film having a first face and a second face, a circuit pattern layer including a plurality of bond fingers and ball lands, and a cover coat covering the circuit pattern and selectively exposing the plurality of ball and ball.
Abstract: There is provided a semiconductor package and method for fabricating the same. An embodiment of the semiconductor package includes: a semiconductor chip having a first face and a second face, the first face having a plurality of input/output pads formed thereon; a circuit board composed of a resin film having a first face and a second face, a circuit pattern layer including a plurality of bond fingers and ball lands, and a cover coat covering the circuit pattern layer and selectively exposing the plurality of bond fingers and ball lands, the circuit pattern layer being formed on the first face of the resin film, the circuit board having a through hole at the center thereof, the semiconductor chip being placed in the through hole; electrical connection means for electrically connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board; an encapsulant for encapsulating the semiconductor chip, connection means and a part of the circuit board; and a plurality of conductive balls fused to the circuit board. Accordingly, the semiconductor package becomes very thin and its heat spreading performance is improved.
345 citations
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15 Mar 2006TL;DR: In this article, damage pre-cursors based residual life computation approach for various package elements to prognosticate electronic systems prior to appearance of any macro-indicators of damage has been presented.
Abstract: In this paper, damage pre-cursors based residual life computation approach for various package elements to prognosticate electronic systems prior to appearance of any macro-indicators of damage has been presented. In order to implement the system-health monitoring system, precursor variables or leading indicators-of-failure have been identified for various package elements and failure mechanisms. Model-algorithms have been developed to correlate precursors with impending failure for computation of residual life. Package elements investigated include, first-level interconnects, dielectrics, chip interconnects, underfills and semiconductors. Examples of damage proxies include, phase growth rate of solder interconnects, intermetallics, normal stress at chip interface, and interfacial shear stress
331 citations
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07 Apr 1999TL;DR: In this article, a thin, stackable semiconductor package having improved electrical and heat dissipating performance comprises a semiconductor chip having an integrated circuit and a plurality of input/output pads on a surface thereof.
Abstract: A thin, stackable semiconductor package having improved electrical and heat dissipating performance comprises a semiconductor chip having an integrated circuit and a plurality of input/output pads on a surface thereof. A lead frame having a plurality of inner leads with upper and a lower surfaces has one of those surfaces bonded to a surface of the chip with a bonding agent. The leads each has a projection formed on at least one of the upper and lower surfaces at a distal end portion of the lead. Each of the leads is electrically connected to an associated input/output pad of the chip through a wire bonding process using electrically conductive wires, or by a ball bonding process using electrically conductive balls. Alternatively, the leads may be directly bonded to the input/output pads of the chip by a TAB bonding process. An encapsulated portion envelops the semiconductor chip and the leads while exposing the projections of the leads to the atmosphere outside the encapsulated portion. A solder ball is welded to the bottom surface of the projection of each lead and is used as a signal input/output terminal of the package. A chip heat sink may be bonded to the chip to further increase the capacity of the package to dissipate heat away from the chip during operation.
320 citations
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14 Jun 1999TL;DR: In this paper, an integrated circuit die and the methods and leadframes for making such packages are disclosed and a method of making a package includes providing a metal leadframe having a die pad in a rectangular frame.
Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.
316 citations
Authors
Showing all 1070 results
Name | H-index | Papers | Citations |
---|---|---|---|
Thomas P. Glenn | 48 | 130 | 6676 |
Dong-Hoon Lee | 48 | 762 | 23162 |
Joungho Kim | 40 | 579 | 7365 |
Steven Webster | 34 | 83 | 3322 |
Young Bae Park | 33 | 216 | 4325 |
Roy Dale Hollaway | 28 | 53 | 2324 |
Ronald Patrick Huemoeller | 26 | 91 | 2385 |
Robert Francis Darveaux | 23 | 70 | 1881 |
MinJae Lee | 23 | 99 | 3083 |
Il Kwon Shim | 21 | 41 | 1403 |
Vincent DiCaprio | 20 | 27 | 1973 |
Sukianto Rusli | 19 | 44 | 1308 |
Glenn A. Rinne | 19 | 34 | 898 |
Ahmer Syed | 18 | 55 | 1192 |
David Jon Hiner | 18 | 54 | 1173 |