Institution
Applied Micro Circuits Corporation
About: Applied Micro Circuits Corporation is a based out in . It is known for research contribution in the topics: Signal & Clock signal. The organization has 367 authors who have published 581 publications receiving 6701 citations. The organization is also known as: AMCC & AppliedMicro.
Papers published on a yearly basis
Papers
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11 Apr 2001TL;DR: In this paper, a system and method have been provided for sorting information segments in a packet/cell earliest deadline first queue circuit, which permits information segments to be inserted at a rate that is twice as fast as the maximum extraction rate.
Abstract: A system and method have been provided for sorting information segments in a packet/cell earliest deadline first queue circuit. The invention permits information segments to be inserted at a rate that is twice as fast as the maximum extraction rate. Pairs of permanent and temporary registers are organized into a hierarchical sequence of stages. Generally, information segments with lower field ranks move systolically through the stages to temporary registers in higher sequence stages. Information segments with higher field ranks move systolically through the stages to permanent registers lower in the sequence of stages. The invention permits the highest rank information segments to be sorted and extracted with great efficiency.
900 citations
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14 Feb 2002TL;DR: In this paper, a Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window.
Abstract: A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe base is made at an extrinsic area, underneath the base electrode, after removal of the sacrificial oxide. The SiGe is covered with a temporary oxide layer during further processes, and this protective layer is removed immediately before the deposition of the emitter material. The selective deposition of the SiGe at a relatively late stage of the fabrication process helps insure that the film remains free of the stresses which can degrade electron mobility. A process of fabricating the above-described HBT device is also provided.
118 citations
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26 Mar 2002TL;DR: In this paper, a high speed flexible interconnect cable includes a number of conductive layers and dielectric layers to form one or more high speed electrical transmission line structures, such as a grounded coplanar waveguide, a microstrip structure, a stripline structure, or the like.
Abstract: A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure, a microstrip structure, a stripline structure, or the like. The cable can be coupled to destination components using a variety of connection techniques, e.g., direct bonding to a circuit substrate, direct soldering to a flip chip, mechanical attachment to a component, or integration with a circuit substrate. The cable can also be terminated with any number of known or standardized connector packages, e.g., SMA, GPPO, or V connectors.
100 citations
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18 Jul 1996TL;DR: In this paper, the authors propose a memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible master data path for the transfer data from the master to the slave data path.
Abstract: A memory interface unit comprising a bus interface unit, a buffer which can store multiple data burst subsets in transit to or from a digital memory, and a switch which includes an externally accessible master data path for the transfer data to or from the bus interface unit and which includes an externally accessible slave data path for the transfer of data to or from the buffer and which includes a direct data path for the transfer data between the bus interface unit and the buffer.
81 citations
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04 Sep 2002TL;DR: In this paper, a server load balancing method is provided for making the load of each server uniform, which includes a server pool definition unit of storing the information on plural servers as server pool, a processing status storing unit of providing a status for each server, and a request distributing unit of breaking a series of requests received from the client and sending each request to the server with the least load on the request-receiving time.
Abstract: A server load balancing method is provided for making the load of each server uniform. The server load balancing method is arranged to include a server pool definition unit of storing the information on plural servers as a server pool, a processing status storing unit of storing a processing status of each server, and a request distributing unit of breaking a series of requests received from the client and sending each request to the server with the least load on the request-receiving time.
79 citations
Authors
Showing all 367 results
Name | H-index | Papers | Citations |
---|---|---|---|
Cengiz S. Ozkan | 47 | 297 | 8920 |
NJ Nico Dam | 22 | 116 | 1698 |
Ezra Robert Gold | 15 | 40 | 1070 |
Subhash C. Roy | 15 | 44 | 634 |
P.C. Maulik | 13 | 27 | 591 |
Shi Cheng | 12 | 24 | 373 |
Abhishek Agrawal | 12 | 39 | 340 |
Sushil Singh | 11 | 19 | 716 |
Jeffrey Thomas Smith | 10 | 14 | 377 |
Robert J. Schuelke | 10 | 24 | 943 |
Alan Michael Sorgi | 9 | 30 | 294 |
Alexander Joffe | 9 | 16 | 333 |
Satish Sathe | 8 | 16 | 247 |
James Leroy Blair | 8 | 10 | 300 |
Ivana Djurdjevic | 8 | 19 | 246 |