Showing papers by "Center for Discrete Mathematics and Theoretical Computer Science published in 2021"

Evaluation model of forest eco economic benefits based on discrete particle swarm optimization

Abstract: In order to evaluate the comprehensive benefits of forest ecological economy, a model based on discrete particle swarm optimization is proposed First of all, the discrete particle swarm optimization algorithm is defined and introduced into the evaluation parameters of forest ecological and economic benefits for internal processing, and the evaluation model of forest ecological and economic benefits is constructed Optimize the system evaluation of the model, continuously develop the internal model structure adjustment operation, and finally obtain the experimental data needed by the system The experimental results show that the model based on the discrete particle swarm optimization algorithm has better convergence, better optimization and robustness, and has higher practical application value

Existence and global exponential stability of periodic solutions for feedback control complex dynamical networks with time-varying delays

Abstract: This paper focuses on the existence and global exponential stability of periodic solutions for feedback control complex dynamical networks with time-varying delays (FCCDND). Combining the continuation theorem of coincidence degree theory, a combinatorial identity about Kirchhoff’s matrix tree theorem in graph theory, and Lyapunov method, a novel method is established to investigate the existence and global exponential stability of periodic solutions for FCCDND. Finally, the effectiveness and practicability of our results are illustrated by a numerical example and its simulation.

Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints

Abstract: Modern FPGAs often contain heterogeneous architectures and clocking resources which must be considered to achieve desired solutions. As the design complexity keeps growing, placement has become critical for FPGA timing closure. In this paper, we present an analytical placement algorithm for heterogeneous FPGAs to optimize its worst slack and clock constraints simultaneously. First, a heterogeneity-aware and memory-friendly delay model is developed to accurately and rapidly assess each connection delay. Then, a two-stage clock region refinement method is presented to effectively resolve the clock and resource violations. Finally, we develop a novel timing-based co-optimization method to generate optimized placement without any clocking violations. Compared with the state-of-the-art placer based on the advanced commercial tool Xilinx Vivado 2019.1 with the Xilinx 7 Series FPGA architecture, our algorithm achieves the best worst slack and routed wirelength while satisfying all clock constraints.

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

Abstract: As one of the most important routing problems in the complex network within a very-large-scale integration (VLSI) circuit, bus routing has become much more challenging when witnessing the advanced technology node enters the deep nanometer era because all bus bits need to be routed with the same routing topology in the context. In particular, the nonuniform routing track configuration and obstacles bring the largest difficulty for maintaining the same topology for all bus bits. In this paper, we first present a track handling technique to unify the nonuniform routing track configuration with obstacles. Then, we formulate the topology-aware single bus routing as an unsplittable flow problem (UFP), which is integrated into a negotiation-based global routing to determine the desired routing regions for each bus. A topology-aware track assignment is also presented to allocate the tracks to each segment of buses under the guidance of the global routing result. Finally, a detailed routing scheme is proposed to connect the segments of each bus. We evaluate our routing result with the benchmark suite of the 2018 CAD Contest. Compared with the top-3 state-of-the-art methods, experimental results show that our proposed algorithm achieves the best overall score regarding specified time limitations.

Iteratively weighted thresholding homotopy method for the sparse solution of underdetermined linear equations

Abstract: Recently, iteratively reweighted methods have attracted much interest in compressed sensing, outperforming their unweighted counterparts in most cases. In these methods, decision variables and weights are optimized alternatingly, or decision variables are optimized under heuristically chosen weights. In this paper, we present a novel weighted $l_1$-norm minimization problem for the sparsest solution of underdetermined linear equations. We propose an iteratively weighted thresholding method for this problem, wherein decision variables and weights are optimized simultaneously. Furthermore, we prove that the iteration process will converge eventually. Using the homotopy technique, we enhance the performance of the iteratively weighted thresholding method. Finally, extensive computational experiments show that our method performs better in terms of both running time and recovery accuracy compared with some state-of-the-art methods.

Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning

Abstract: A parallel simulation that partitions a large circuit into sub-circuits is widely used to reduce simulation runtime. To achieve higher simulation throughput, we shall consider signal directions, and thus the final partitioning solution must be acyclic. In this paper, we model a circuit as a directed graph and consider acyclic graph partitioning to minimize edge cuts. This problem differs from the traditional partitioning problem because of the additional acyclicity constraint. Unlike traditional heuristics that tend to be trapped in local minima, especially for large graphs, we present a novel discrete dynamic filled function algorithm for the acyclic graph partitioning problem. Our algorithm can guarantee convergence and effectively move from one discrete local minimizer to another better one. Experimental results show that our algorithm achieves 8% average cutsize reduction over the state-of-the-art works in a comparable runtime.

An Adaptive Multimeme Memetic Algorithm for the VLSI Standard Cell Placement Problem

Abstract: Placement has a tremendous impact on the final performance of a VLSI chip, and the problem itself is a combinatorial optimization problem. Memetic algorithms with problem-specific designs can solve the problem with high quality solutions, but they are generally time-consuming. To address this issue, adopting an adaptive strategy has become a key way to reduce the runtime of a memetic algorithm. In this paper, we present an adaptive multimeme memetic algorithm (AMMA) for the VLSI standard cell placement problem. In accordance with the distinctive features of the solution space of the problem, we propose a set of adaptive strategies to greatly improve the runtime efficiency. The main novelty of the proposed strategy lies in its constructing of crossover multimeme and the acceptance criteria of placement candidates. The experimental results and comparisons on Peko suite3 and ISPD04 benchmark circuits verified the efficacy and efficiency of the proposed adaptive strategies. Compared to the memetic algorithm without these main adaptive strategies, the AMMA reduces the runtime by around 32.58% on average.

A dynamic graph-based approach to ranking firms for identifying key players using inter-firm transactions

Abstract: Ranking firms in an inter-firm transaction network is a crucial task for identifying key players in an industry, thereby explaining the agglomeration of economic activities and assisting with competitor identification. To the best of our knowledge, despite the advantages of network-based approaches in market analysis, few studies have employed network analysis tools to rank firms. However, these studies failed to capture the characteristics of inter-firm transaction networks (i.e., evolving over time, having multiple edges between nodes, among others). In this study, we propose a new ranking method, FirmRank, that identifies key players based on centrality metrics in network analysis, leveraging inter-firm transactions to discern the characteristics of an inter-firm transaction network. Our proposed ranking method is evaluated using real-world datasets from a corporate information database, and the evaluation results demonstrate the superiority of our method over well-known ranking methods—PageRank and age-based PageRank.

Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection

Abstract: The data imbalance problem often occurs in nanometer VLSI applications, where normal cases far outnumber error ones. Many imbalanced data handling methods have been proposed, such as oversampling minority class samples and downsampling majority class samples. However, existing methods focus on improving the quality of minority classes while causing quality deterioration of majority ones. In this paper, we propose a two-stage classifier to handle the data imbalance problem. We first develop an iterative neural network framework to reduce false alarms. Then the oversampling method on a final classification network is applied to predict the two classes better. As a result, the data imbalance problem is well handled, and the quality deterioration of majority classes is also reduced. Since the iterative stage does not change any existing network structure, any convolutional neural network can be used in the framework. Compared with the state-of-the-art imbalanced data handling methods, experimental results on the hotspot detection problem show that our two-stage classification method achieves the best prediction accuracy and reduces false alarms significantly.

Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification

Abstract: With the continued feature-size shrinking in modern circuit designs, the layout performance estimation and parasitic import calculation based on the extracted centerline result play an important role in mask verification. Most previous works on layout centerline extraction focus on identifying the connectivity among the devices in a mask layout, with few ones collecting accurate centerline information for mask verification while considering design constraints. In this paper, we first formulate the centerline extraction problem as a Voronoi diagram to collect centerline points. Then, we present a graph-based invalid centerline removal algorithm to generate an initial centerline result. Finally, a complexity-driven centerline optimization method is proposed to further optimize the centerline while considering design constraints. Compared with the commercial 3D-RC parasitic parameter extraction tool RCExplorer and the 1st place in the 2019 EDA Elite Challenge Contest, experimental results show that our algorithm achieves the highest average precision ratio of 99.8% on centerline extraction while satisfying all design constraints in the shortest runtime.

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints

Abstract: The modern FPGA placement problem has become much more challenging than ever with various emerging design constraints, such as the location (including relative location (RLOC) and location range) and chain constraints, which have not been considered in the literature. In this paper, we propose a combinatorial algorithm for FPGA legalization with location and chain constraints. We first identify a virtual range to cluster an instance with the RLOC constraint and formulate minimum cost integer linear programming. Besides, we use an adaptive algorithm to deal with the chain-aware legalization problem for better quality and runtime trade-offs. Finally, a legalization algorithm based on minimum cost maximum flow (MCMF) is used to improve the solution quality further. Compared with the state-of-the-art work, experimental results show that our proposed algorithm can achieve respectively 4.4% and 4.9% smaller average and maximum movements, 1.7% smaller routed wirelength, and 7.6% shorter routing runtime