Showing papers by "Codex Corporation published in 1983"

The OSI reference model

Abstract: The early successes of computer networks in the mid-1970's made it apparent that to utilize the full potential of computer networks, international standards would be required. In 1977, the International Standards Organization (ISO) initiated work on Open Systems Interconnection (OSI) to address these requirements. This paper briefly describes the OSI Reference Model. The OSI Reference Model is the highest level of abstraction in the OSI scheme. The paper first describes the basic building blocks used to construct the network model. Then the particular seven-layer model used by OSI is briefly described, followed by a discussion of outstanding issues and future extensions for the model.

Two-pass multiplier/accumulator circuit

Abstract: A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations are carried out by passing the product of the operands successively through an array of adders in the Adder unit 34. Each adder adds an appropriate multiple of the contents of the X Register to the Accumulator 40 or to the output of the previous adder. The multiples are selected according to the contents of the Y Register. The X and Y Registers are fully buffered so that additional data transfers and functions may be performed while an arithmetic operation is in progress in a "pipeline" manner. The circuit is also capable of indicating the maximum or minimum value in a sequence of numbers in response to a single computer instruction to the circuit.

High speed fully precharged programmable logic array

Abstract: A logic array which is small in size and low in power dissipation uses only one clock signal. The array is fully precharged by precharging a first portion and a second portion and then applying ground to the first portion while delayably applying the ground to the second portion. The address is read into the first portion during the precharging to speed up operation of the array.

Dual processor digital modem apparatus

Abstract: Modem apparatus in which a modulated carrier signal represents digital bits, wherein the apparatus includes first digital processing circuitry having first programmable digital circuitry for arithmetic manipulation of digital values in accordance with selectable arithmetic program instructions to produce a correspondence between a sequence of signal values at a rate of 1/T signal values per second and a sequence of samples at a rate higher than 1/T samples per second representing the modulated carrier signal, where T represents the duration of a modulation period of the carrier signal, first bus circuitry connected to the first programmable digital circuitry for carrying the digital values and the arithmetic program instructions, and first memory circuitry connected to the first bus circuitry for storing the instructions, digital values, and signal values; second digital processing circuitry comprising second programmable digital circuitry for generating control signals corresponding to predetermined sequences of the arithmetic instructions, second bus circuitry connected to the second programmable circuitry for carrying the control signals, and second memory circuitry connected to the second bus circuitry for storing control signal program instructions; timing circuitry for timing the operation of the first and second processing circuitries, and means for providing a sequence of time-limited handshakes between the first and second processing circuitries, during which the control signals are transferred to the first processing circuitry to cause the first programmable digital circuitry to carry out the predetermined sequences of the arithmetic instructions.

Zero sensitivity properties of the digital lattice filter

Abstract: The first-order movement of zeros given small perturbations of the PARCOR coefficients in the all-zero digital lattice filter is determined analytically This is an extension of previous work characterizing sensitivity by integral spectral deviation measures, and is of interest since much is known about the perceptual effects of deviations in formant frequency location The principal insight is the role that the frequency of the zero plays in its sensitivity and a better understanding of the quite different sensitivity properties of the first and last PARCOR coefficients Comparison is made to the transversal filter structure, and further interpretation of the effect of preemphasis is given By examining individual terms of the zero sensitivity equations, an understanding may be gained of the factors responsible for large zero movements and the methods which may be used to decrease these movements As an example, a computationally simple bilinear type of transformation of the original PARCOR's to a new set of PARCOR's is proposed, which decreases the zero sensitivity at low frequency and increases it at high frequency The perceptual advantage is estimated by listening tests and spectral deviation plots to be comparable to that of preemphasis, about 2 bits/frame

Modem end of message detector

Abstract: In modem apparatus having receiver circuitry which demodulates a received carrier into a sequence of received signals and decodes each signal into a signal point drawn from a predetermined signal point alphabet, the received carrier being modulated in accordance with a sequence of signal points representing a message, that improvement having circuitry for estimating the receipt of the end of the message by testing each received signal against a predetermined end-of-message condition.