Showing papers by "Codex Corporation published in 1990"

Lattice and trellis-coded quantization

Abstract: Vectors are quantized by representing the vectors by quantized values using a codebook having granular regions which are based on a coset code, and which lie inside a boundary region which is based on another coset code, the boundary region being other than an N-cube and other than the Voronoi region of a sublattice Λ b =MΛ g of a lattic Λ g upon which the granular regions may have been based.

Congestion control for packet voice by selective packet discarding

Abstract: In order to reduce the time delays as well as multiplexer memory requirements in packet voice systems, a family of congestion control schemes is proposed. They are all based on the selective discarding of packets whose loss will produce the least degradation in quality of the reconstructed voice signal. A mathematical model of the system is analyzed and queue length distributions are derived. These are used to compute performance measures, including mean waiting time and fractional packet loss. Performance curves for some typical systems are presented, and it is shown that the control procedures can achieve significant improvement over uncontrolled systems, reducing the mean waiting time and total packet loss (at transmitting and receiving ends). Congestion control with a resume level is also analyzed, showing that without increasing the fractional packet loss, the mean and variance of the queue can be reduced by selecting an appropriate resume level. The performance improvements are confirmed by the results of some informal subjective testing. >

Decision-feedback equalization of time-dispersive channels with coded modulation

Abstract: An extension is presented of the work of V.M. Eyubogin (see ibid., vol.36, p.401-9, Apr. 1988) on decision-feedback equalization (DFE) applied to coded systems with interleaving. The authors study the adaptive implementation of the DFE using recursive-least-squares algorithms (RLS). System performance on time-dispersive channels with nulls as well as on channels with relatively small intersymbol interference is investigated. A reference insertion method is used to improve system performance, and a two-stage processing technique is adopted to use the more reliable decisions from the decoder in equalizer coefficient adaptation. Simulation results show that the RLS-implemented DFE systems with coded modulation can successfully combat severe channel distortion while maintaining the coding gain over corresponding uncoded systems. >

Transmitting encoded data on unreliable networks

Abstract: Information encoded by data compression (or another data encoding technique, e.g., encryption, requiring synchronization between the encoder (12a) and decoder (22b) is transmitted over an unreliable network (16) by checking for transmission errors after decoding. if an error is detected, the encoder (12a) is reset, using a reset protocol, which may operate over an unreliable re-verse channel (16) by using a timer (46) to generate further reset requests when the receiver does not acknowledge them in a timely fashion.

Fast training echo canceller

Abstract: An echo cancellation modem having a fast training echo canceller in which the echo cancellation coefficients are computed by taking correlations between a complex, periodic training signal sequence and a real component of the corresponding echo signal. The modem includes a receiver circuit for detecting a signal on a channel possibly including an echo; an echo canceller for estimating the real component of the echo signal; training circuitry for applying the complex training sequence to the channel and for taking correlations between the training sequence and the real component of the corresponding echo signal. The modem also includes a computational element for computing the period of the periodic sequence, generating the complex periodic train sequence in real time and for computing a phase roll frequency based upon the computed echo cancellation coefficients.

Convergence and steady-state behavior of a phase-splitting fractionally spaced equalizer

Abstract: The eigenstructure, the initial convergence, and the steady-state behavior of a phase-splitting fractionally spaced equalizer (PS-FSE) are analyzed. It is shown that the initial convergence rate of a T/3 or, in general, a T/M, PS-FSE employing the least-mean-square (LMS) stochastic gradient adaptive algorithm is half that of a symbol rate equalizer (SRE) or a complex fractionally spaced equalizer (CFSE) with the same time span. It is also shown that the LMS adaptive PS-FSE with symbol rate update converges to a Hilbert transformer followed by a matched filter in cascade with an optimal SRE, and thus forms an optional receiver structure. The LMS PS-FSE is computationally more efficient and introduces less system delay than the CFSE. >

Digital speech coder having improved long term lag parameter determination

Abstract: A method and apparatus is provided for determining the lag of a long term filter in a code excited linear prediction speech coder. An open loop lag is first determined using an autocorrelation function. The open loop lag is then utilized to generate a limited range over which a closed loop search is performed. The range for appropriate values includes lags that are harmonically related to the open loop lag as well as adjacent lags.

Partial response channel signaling systems

Abstract: Apparatus for generating a (running digital sum) sequence of digital signals Xk and/or a (partial response coded) sequence of digital signals Yk, K=1, 2, . . . , such that Yk =Xk ±Xk-l, L and integer, in which the Yx signals are a sequence in a given modulation code. In one aspect, the signals Yk are chosen to be congruent to coset representatives specified in accordance with a modulation code, a plurality of code constellations are used, and at least one constellation includes both a point with a positive sum of coordinates and one with a negative sum of coordinates. In another aspect, the signals Xk are chosen to be congruent to a sequence of alternate (precoded) coset representatives. In other aspects, the Yk alphabet signals are evenly spaced, and a selectable, e.g., an optimal, tradeoff between Sx and Sy is made. An N-dimentional modulation code is generated as a sequence of one-dimensional signals. A maximum likelihood sequence estimation decoder reconstructs the estimated running digital sum, and generates a signal whenever the estimated running digital sum is outside a permissible range. In another aspect, the decoder includes a modified maximum likelihood sequence estimator adapted to find MQ partial decoded sequences, where Q is the number of encoder states, and M is an integer.

Method of making printed circuit board assembly

Abstract: A first set of plated-through holes in the printed circuit board (PCB) are covered by a protective solder mask on the solder side of the PCB while a second set of plated-through holes are exposed. Electrical components are disposed on the component side with leads inserted in the second set of holes. Solder is prevented from flowing into the first set of holes during wave soldering by the mask covering. Conductive pins designed for press fitting into the first set of holes are inserted therethrough to define connecting pins on each side of the PCB following wave soldering. This permits both a wave soldering and press fit operation to be accommodated.

Controlling clock frequencies in a communications network

Abstract: The frequency of a clock for a receiving terminal is controlled based on a predetermined clock frequency of a terminal that produces a continuous stream of data at a predetermined frequency for transmission to the receiving terminal over a communications network of the kind in which data is transmitted between the terminals in discrete packets that are delayed on the network by possibly different amounts. Arrivals of packets that are sent to the receiving terminal are detected, time intervals between the arrivals of successive packets are determined, and the time intervals are processed to generate an estimate that is related to the predetermined frequency. The frequency of the receiving terminal clock is controlled in response to the estimate.

Frame loss due to buffer overflows in fast packet networks

Abstract: An analytical method is derived to estimate the protocol data unit (PDU) frame loss probability as a function of buffer size when identical sources are multiplexed on a fast packet link. The generation of PDUs from each source is governed by an on-off source model, and upper and lower bounds on the frame loss probability are derived. The analysis takes into account the correlated nature of fast packet losses within a PDU due to buffer overflows. The required buffer size for a given frame loss probability is directly proportional to the expected PDU frame length, and the loss probability decreases exponentially with increasing buffer size. >

Fixed-prefix encoding of the integers can be Huffman-optimal

Abstract: Various source coding schemes encode the set of integers using a binary representation of the integers to be encoded, prefixed by some information about the length of that representation. In the context of recency rank encoding, these can be regarded as attempts to assign codewords with lengths close to the logarithm of the integer to be encoded, or as attempts to construct a code for a distribution function Q(*) on the integers, where Q(k)=(1/k)/ Sigma /sub i/(1/i), i in I, and I is a finite set of positive integers to be encoded. It is shown that fixed-prefix encoding is equivalent to Huffman coding for the distribution Q(*). >

Correlation-based fast training of data-driven Nyquist in-band echo cancellers

Abstract: A novel echo canceller fast training scheme for data-driven 'Nyquist' in-band echo cancellers is presented. This scheme simultaneously estimates the near and far echo canceller coefficients by sending a special periodic training sequence and correlating a segment of the sequence with the real echo samples of the sequence. The requirements and the generation of such a training sequence are discussed and described in detail. Fast initialization of a phase-roll compensator is also discussed. The proposed scheme is compared with other echo canceller training schemes. >

A new complex system identification method and its application to echo canceller fast initialization

Abstract: A method is proposed for estimating the impulse response of a complex system based on its complex input and only the real part of its output. A unique periodic white complex testing sequence is constructed, and it is then sent to the system to be estimated. An important feature of the testing sequence is that its real and imaginary parts are mutually orthogonal, i.e. their cross-correlation is zero. Due to this orthogonality, the effects of the system's real imaginary parts are ideally decoupled. The cross-correlation between the complex testing sequence and the system's real part output yields an accurate estimate of the system's complex impulse response. In applications where the unknown system's impulse response is sparse, it is possible to squeeze it and choose a considerably small period for the sequence to reduce complexity. An effective algorithm for this purpose is presented. The application of this new method to fast training of the Nyquist echo cancellers in data modems is described. It is shown that using these techniques, fast and accurate estimation can be achieved efficiently. >

Voice packet loss: destination vs. internodal links

Abstract: An investigation is made of voice packet loss behavior at both the destination and internodal links in a packet switched network. The fractional loss and blocking time periods for both are derived using a bivariate Markov model. The numerical results show that blocking due to the delay constraint at the destination can result in long periods of consecutive packet loss, which seriously degrade voice quality. This work indicates that the packets with excessive delay should be discarded at the internodal links, instead of blocked at the destination. The relation between the internodal link buffer size and end-to-end permissible queuing delay is established. >

Over speed data rate adjustment method and apparatus in an asynchronous data stream

Abstract: An improved process handles asynchronous data in which certain stop bits have been deleted or extra stop bits added to accommodate speed differences between a data source and the asynchronous data stream rate. A second asynchronous data stream is generated based upon said first data stream. Upon detecting a missing stop bit, a shortened stop bit is generated in the second data stream and a predetermined number of subsequent stop bits are also shortened to achieve synchronization with the first data stream. In a preferred embodiment, the receipt of an extra stop bit in the first data stream while shortened stop bits are being generated results in the extra stop bit not being generated in the second data stream and a corresponding flag set. If another missing stop bit occurs while shortened stop bits are being generated and if the flag is set, a shortened stop bit is inserted and the flag is reset.

Channel reuse multiple access protocol for bidirectional bus networks

Abstract: A novel contention-free multiple-access protocol for bidirectional-passive bus packet networks is proposed. One version has a simple fixed-assignment transmission scheduling similar to that of the time-division multiple-access protocol, except that left-going and right-going packets may be transmitted only in alternate rounds. Another version employs a simple reservation scheme to provide demand-assignment transmission scheduling. In either instance the protocol may offer a maximum throughput exceeding one packet per packet transmission time under appropriate conditions, where throughput is defined as the number of distinct packets transmitted successfully per packet transmission time. This is possible through channel reuse as explained. >

Apparatus for generating sequences of digital signals

Abstract: Apparatus is described for generating a sequence of digital signals xk and/or a sequence of digital signals yk, k = 1, 2, ..., such that yk = Σj≧0 fjxk-j, in which the yk signals are a sequence in a given modulation code. In one arrangement, the signals yk are chosen to be congruent to coset representatives specified in accordance with a modulation code, a plurality of code constellations are used, and at least one constellation include both a point with a positive sum of coordinates and one with a negative sum of coordinates.

A custom VLSI architecture for the CCITT wideband coding standard

Abstract: A custom VLSI architecture for implementing the CCITT G.722 64-kb/s (7-kHz) wideband audio coding standard is presented. By tailoring the architecture to the algorithm, an architecture was designed that is capable of processing a full duplex channel in less than 625 cycles. That is 71-73% less cycles than are required by the reported general-purpose DSP implementations. In a 1.5- mu technology with a 100-ns cycle time, it is estimated that the architecture would consume 95000 mL/sup 2/ of silicon and support two full duplex channels on a single chip. The authors wrote a behavioral simulation of the architecture and its implicit microcode. This simulates the architecture's behavior at the bit level. The simulation passes the CCITT G.722 test vectors, demonstrating that the implementation conforms to the standard. >

A custom VLSI architecture for the CCITT wideband coding standard

Abstract: A custom VLSI architecture for implementing the CCITT G.722 64-kb/s (7-kHz) wideband audio coding standard is presented. By tailoring the architecture to the algorithm, an architecture was designed that is capable of processing a full duplex channel in less than 625 cycles. That is 71-73% less cycles than are required by the reported general-purpose DSP implementations. In a 1.5- mu technology with a 100-ns cycle time, it is estimated that the architecture would consume 95000 mL/sup 2/ of silicon and support two full duplex channels on a single chip. The authors wrote a behavioral simulation of the architecture and its implicit microcode. This simulates the architecture's behavior at the bit level. The simulation passes the CCITT G.722 test vectors, demonstrating that the implementation conforms to the standard. >

Spectral estimation of nonuniformly sampled data using an interpolation technique

Abstract: A standard technique for estimating the spectrum of a nonuniformly sampled signal is to first estimate a set of uniformly sampled correlation coefficients and then calculate the power spectrum of the signal as the discrete Fourier transform (DFT) of the correlation sequence. In the popular correlation slotting technique, the average of all the samples in a chosen slot is used to compute the correlation value. In the proposed technique, the value of the signal at a desired location is obtained using a linear interpolation technique. Bias in the spectral estimate due to interpolation is determined using theoretical analysis, and variance is estimated using simulation studies. The new method requires fewer computations than the slotting technique to yield a specified accuracy. >