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Showing papers by "Codex Corporation published in 1994"


Patent
11 Apr 1994
TL;DR: In this article, a high speed modem with a logical link negotiation unit (102) for probing and determining data compression parameters (DCPs) for a synchronous data compression link with a remote modem and inserting the DCPs and predetermined instructions into compressed data.
Abstract: The present invention provides a novel scheme for automatically increasing data throughput in a communication system by having data compression with delay minimization done with a modem. A high speed modem includes a logical link negotiation unit (102) for probing and determining data compression parameters (DCPs) for a synchronous data compression link with a remote modem and for inserting the DCPs and predetermined instructions into compressed data. The modem also includes a physical layer connection unit (104) coupled to synchronous data terminal equipment to provide a delay minimizing scheme that adjustably accommodates data delivery delay to the receiving modem. A method and system incorporate the functions of the high speed modem.

46 citations


Journal ArticleDOI
TL;DR: This paper presents a composite performance index for communication networks with variable link-capacities based on link reliabilities and multiple-capacity link-states, useful for determining the performance of networks with links operating with residual traffic-carrying capacity.
Abstract: This paper presents a composite performance index for communication networks with variable link-capacities. This index is based on link reliabilities and multiple-capacity link-states. Source-to-terminal success is the ability to provide connectivity with a certain traffic-carrying capacity. This index is useful for determining the performance of networks with links operating with residual traffic-carrying capacity and gives a good idea of the available resources for a particular s-t connection. An algorithm is given to evaluate the composite performance index. >

33 citations


Patent
Craig S. Holt1
18 Aug 1994
TL;DR: In this paper, a serial string of FIFO cells propagates data from input to output by sending request and acknowledge signals between adjacent cells, and the acknowledge signal indicates completion of the transfer.
Abstract: A FIFO (10) uses a fill indicator circuit (20) to indicate a fill status and provide control signals to a data source and data sink to cease operation. A serial string of FIFO cells (14) propagates data from input to output by sending request and acknowledge signals between adjacent cells. The request signal initiates data transfer to the next logical cell and the acknowledge signal indicates completion of the transfer. The fill indicator has one cell for each FIFO cell for monitoring the request and acknowledge signals looking for predetermined state sequences to indicate whether each FIFO cell is full or empty.

22 citations


Patent
08 Aug 1994
TL;DR: In this article, a communication system transmits packetized voice data from a voice source (102) to a voice destination (110) at the voice destination, the packets are accumulated in a buffer (208), sequentially played out and the time the packet waits in the buffer ( 208) is monitored.
Abstract: A communication system transmits packetized voice data from a voice source (102) to a voice destination (110). At the voice destination (110), the packets are accumulated in a buffer (208), sequentially played out and the time the packet waits in the buffer (208) is monitored. The time future voice packets are played out is accordingly adjusted.

20 citations


Journal ArticleDOI
TL;DR: Computer simulation results show that when the echo path shows significant nonlinearity the layered form is effective in improving the echo cancellation performance with reduced computational complexity.
Abstract: The authors propose a layered bilinear filter structure, and study its performance in an adaptive echo cancellation framework for high speed data transmission with precoding. In their application, they mainly consider the reduced order situations where the number of coefficients used in the echo canceller is less than that in the echo path. Computer simulation results show that when the echo path shows significant nonlinearity the layered form is effective in improving the echo cancellation performance with reduced computational complexity. Using bilinear echo cancellation with a small number of coefficients, echo return loss enhancement (ERLE) over the linear case improves by about 15 dB at a signal-to-noise ratio of 30 dB. >

19 citations


Patent
Lin Jingdong1
12 Dec 1994
TL;DR: In this paper, a detector (100) determines whether an input signal (10) comprises a first signal or a second signal by comparing (60) the first distance to the second distance.
Abstract: A detector (100) determines whether an input signal (10) comprises a first signal or a second signal. A first local signal (207) is generated based on the first signal and a second local signal (307) is generated based on the second signal. A first error (211) is formed based on the first local signal and a scaled input signal (50), and a second error (311) is formed based on the second local signal and the scaled input signal. A first distance (215) between the scaled input signal and the first local signal is formed based on the first error, while a second distance (315) between the scaled input signal and the second local signal is formed based on the second error. Whether the input signal comprises the first signal or the second signal is determined by comparing (60) the first distance to the second distance.

12 citations


Patent
19 Aug 1994
TL;DR: In this article, the maximum length string test is performed by testing a string length counter for the value zero, where the length of the input string is equal to a predetermined maximum string length, and the string matching process is terminated without processing an additional character that would cause an unsuccessful string match.
Abstract: A method (100) and device (200) increase efficiency of a data compression encoder or decoder by testing whether an input string is a maximum length string upon successful match of the input string in a dictionary. Where the length of the input string is equal to a predetermined maximum string length, the string matching process is terminated without processing an additional input character that would cause an unsuccessful string match. The maximum length string test is accomplished by testing a string length counter for the value zero, where the string length counter is set to the maximum string length value when the input string is NULL or alternatively is set to the maximum string length minus one when the input string is a one character string, and the string length counter is decremented for each input character that extends the matched input string.

12 citations


Journal ArticleDOI
Mei Yong1
TL;DR: The paper presents a new LPC interpolation technique, based on interpolating the impulse response of the LPC synthesis filter, and demonstrates that this method offers a significant complexity reduction for the codebook search over other typical interpolation schemes.
Abstract: In low rate code-excited linear predictive (CELP) coders, the LPC spectral information is usually quantized and transmitted on a frame-by-frame basis about every 20 to 30 msec. The quality of speech reproduced by a CELP coder can be improved by making spectral transitions as smooth and continuous as possible. One way in which this can be accomplished without increasing the transmission bit rate is to interpolate the LPC spectral parameters between adjacent extraction frames. This, however, usually leads to a dramatic increase in the computations required for the codebook search. The paper presents a new LPC interpolation technique, based on interpolating the impulse response of the LPC synthesis filter. It demonstrates that this method offers a significant complexity reduction for the codebook search over other typical interpolation schemes. Furthermore, the experiments show that the coder using the impulse response for interpolation produces the same speech quality as the coder using the LSP parameters for interpolation, and both these parameter sets are superior to other LPC representations for interpolation. >

12 citations


Patent
17 Mar 1994
TL;DR: In this paper, a phase lock loop (10) monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first signal using a programmable divider (30).
Abstract: A phase lock loop (10) monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal A programmable divider (30) latches (60) a program integer for providing a latch integer, compares (64) the latch integer to a constant integer, and generates a flag signal having a first state when the latch integer mismatches the constant integer and a second state when the latch integer matches the constant integer The latch integer is decremented (62) when the flag signal has the first state The flag signal is delayed in response to first and second clock signals for providing the second digital signal having a frequency determined by the program integer The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal

10 citations


Patent
20 Dec 1994

4 citations



Patent
15 Sep 1994
TL;DR: In this paper, a CAM array (50,52,54,56) is arranged in a serpentine configuration to reduce track layout, and a column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array.
Abstract: A data compressor (14) generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table (22). A data decompressor (16) looks up the codewords for a string match in its vocabulary table. The CAM array (50,52,54,56) is arranged in a serpentine configuration to reduce track layout. A column priority encoder (74) reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop (122) with a common control circuit to transfer and refresh data through the flipflop.