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Institution

Codex Corporation

About: Codex Corporation is a based out in . It is known for research contribution in the topics: Network packet & Signal. The organization has 189 authors who have published 241 publications receiving 32205 citations.


Papers
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Patent
20 May 1993
TL;DR: In this paper, a phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency, by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage.
Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

38 citations

Journal ArticleDOI
01 Apr 1985
TL;DR: The article describes a series of congestion related performance difficulties in a TCP/IP network at Ford Aerospace, and suggested some "cures", but fails to address the root causes of the performance difficulties that Mr Nagle discusses.
Abstract: The article "Congestion control in IP/TCP Internetworks" by John Nagle is an excellent illustration of problems inherent in Arpanet and Milnet technology. The article describes a series of congestion related performance difficulties in a TCP/IP network at Ford Aerospace, and suggested some "cures".What in fact the article describes is what appear to be adequate "band-aids" for the basic inadequacies of Arpanet technology. However, it fails to address the root causes of the performance difficulties that Mr. Nagle discusses. It is suggested that all of these problems result from an uncritical adherence to the Arpanet paradigm, without regard to the research and standardization work of the past 15 years.

38 citations

Journal ArticleDOI
TL;DR: In this paper, the eigenstructure, the initial convergence, and the steady-state behavior of a phase-splitting fractionally spaced equalizer (PS-FSE) are analyzed.
Abstract: The eigenstructure, the initial convergence, and the steady-state behavior of a phase-splitting fractionally spaced equalizer (PS-FSE) are analyzed. It is shown that the initial convergence rate of a T/3 or, in general, a T/M, PS-FSE employing the least-mean-square (LMS) stochastic gradient adaptive algorithm is half that of a symbol rate equalizer (SRE) or a complex fractionally spaced equalizer (CFSE) with the same time span. It is also shown that the LMS adaptive PS-FSE with symbol rate update converges to a Hilbert transformer followed by a matched filter in cascade with an optimal SRE, and thus forms an optional receiver structure. The LMS PS-FSE is computationally more efficient and introduces less system delay than the CFSE. >

37 citations

Patent
Yosef Linde1
19 Nov 1981
TL;DR: In this article, a combination for executing a do loop without requiring "overhead" steps to be included in the do loop, having means for determining when the final do loop step is being executed, means for counting the number of do loop iterations remaining, and means for proceeding to the first do-loop step each time the final loop step was being executed provided the last iteration has not been reached, or otherwise for exiting from the doloop.
Abstract: In a programmable machine, a combination for executing a do loop without requiring "overhead" steps to be included in the do loop, having means for determining when the final do loop step is being executed, means for counting the number of do loop iterations remaining, and means for proceeding to the first do loop step each time the final do loop step is being executed provided the last iteration has not been reached, or otherwise for exiting from the do loop.

37 citations

Patent
07 Apr 1995
TL;DR: In this article, the CAM array is arranged in a serpentine configuration to reduce track layout and a column priority encoder reverses the priority of alternate rows to maintain the logical flow through the array.
Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer and refresh data through the flipflop.

37 citations


Authors

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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20133
20111
19991
19951
199412