Codex Corporation

About: Codex Corporation is a based out in . It is known for research contribution in the topics: Signal & Network packet. The organization has 189 authors who have published 241 publications receiving 32205 citations.

Coded modulation system with a simplified decoder capable of reducing the effects of channel distortion

Abstract: A receiver for deciding which signal points were sent from a transmitter based on corresponding noise affected signals received via a distorting channel, the noise affected signals carrying information about a particular sequence of encoding states occupied in a succession of time intervals by a finite state process having a finite number of possible encoding states, the receiver including modifying circuitry for generating a plurality of different modified versions of each received signal, and a decoder for deciding which signal points were sent based on estimating a particular sequence of decoder states by storing a number of path histories of previous signal points and using the modified versions to extend the path histories, the different modified versions of each received signal numbering fewer than the number of stored path histories. In other aspects, the constellation of signal points is partitioned into decision subsets, each possible transitions from a possible decoder state are associated with a decision subset, based on the signal points in the path histories, and each of the modified versions is associated with one of the decision subsets; there are fewer modified versions than the number of decoder states; and the decoder states number fewer than the number of decoder states in an optimum trellis decoder.

Digital speech coder having improved long term lag parameter determination

Abstract: A method and apparatus is provided for determining the lag of a long term filter in a code excited linear prediction speech coder. An open loop lag is first determined using an autocorrelation function. The open loop lag is then utilized to generate a limited range over which a closed loop search is performed. The range for appropriate values includes lags that are harmonically related to the open loop lag as well as adjacent lags.

Partial response channel signaling systems

Abstract: Apparatus for generating a (running digital sum) sequence of digital signals Xk and/or a (partial response coded) sequence of digital signals Yk, K=1, 2, . . . , such that Yk =Xk ±Xk-l, L and integer, in which the Yx signals are a sequence in a given modulation code. In one aspect, the signals Yk are chosen to be congruent to coset representatives specified in accordance with a modulation code, a plurality of code constellations are used, and at least one constellation includes both a point with a positive sum of coordinates and one with a negative sum of coordinates. In another aspect, the signals Xk are chosen to be congruent to a sequence of alternate (precoded) coset representatives. In other aspects, the Yk alphabet signals are evenly spaced, and a selectable, e.g., an optimal, tradeoff between Sx and Sy is made. An N-dimentional modulation code is generated as a sequence of one-dimensional signals. A maximum likelihood sequence estimation decoder reconstructs the estimated running digital sum, and generates a signal whenever the estimated running digital sum is outside a permissible range. In another aspect, the decoder includes a modified maximum likelihood sequence estimator adapted to find MQ partial decoded sequences, where Q is the number of encoder states, and M is an integer.

Synchronizing continuous bit stream oriented terminals in a communications network

Abstract: The frequency of a clock for a receiving terminal is controlled based on a predetermined clock frequency of a terminal that produces a continuous stream of data at a predetermined frequency for transmission to the receiving terminal over a communications network of the kind in which data is transmitted between the terminals in discrete packets that are delayed on the network by possibly different amounts Arrivals of packets that are sent to the receiving terminal are detected, time intervals between the arrivals of the successive packets are determined, and the time intervals are processed to generate an estimate that is related to the predetermined frequency The frequency of the receiving terminal clock is controlled in response to the estimate In one aspect, the time intervals are determined by measuring time differences of arrival between successive packets, and the measured time differences are filtered to generate the estimate In another aspect, the time intervals are determined by measuring phase differences between a reference signal (that indicates the arrival of each packet) and the receiving terminal clock, and the measured phase differences are filtered to generate the estimate

Frequency synthesizer and digital phase lock loop

Abstract: In one aspect the invention features a digital synthesizer having clock circuitry to provide a clock pulse train, synthesizer circuitry to provide a synthesized pulse train at a frequency such that multiple clock pulses occur between pairs of successive synthesized pulses, and phase control circuitry to cause an effective shift in the synthesized pulse train frequency by causing, between pairs of successive synthesized pulses, a number of phase shifts in the clock pulse train.