Codex Corporation

About: Codex Corporation is a based out in . It is known for research contribution in the topics: Network packet & Signal. The organization has 189 authors who have published 241 publications receiving 32205 citations.

High frequency voltage controlled oscillator

Abstract: A phase lock loop (10) operates independent of temperature and process variation by digitally loading a VCO (12) until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors (162-166, 174-180, 182-188) to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit (32) sets the loop node voltage to VDD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector (34) monitors the output frequency of the VCO and passes control signals to a load control circuit (36) to activate digital loads (38) and slow down the VCO to the desired operating frequency.

Network collision detection and avoidance apparatus

Abstract: A technique for regulating the transmission of messages initiated simultaneously by a plurality of nodes of a network, in which clock intervals are established for the network, a sequence of digital values is included in each message and is transmitted to the medium at the rate of one digital value per clock interval, the sequences included in messages that are initiated at the same time by more than one node are transmitted in the same sequence of clock intervals, the presence on the medium of a selected digital value during any clock interval in which a node is transmitting a different digital value within the sequence of a message is detected, and the transmission of the message is interrupted by the node upon such detection, without corrupting another node's transmission.

CMOS input buffer accepting TTL level inputs

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) input buffer circuit is provided which accepts Transistor-Transistor Lock (TTL) input signal levels without generating any significant DC current path. A reference voltage circuit (1, FIG. 1) provides first and second reference voltages (V A and V B , FIG. 1) which are coupled to first and second stages, respectively, of the input buffer circuit (3, FIG. 1), and which are of predetermined magnitudes and scaled relative to each other to permit the P-channel devices of the input buffer circuit to turn off completely when the input to the circuit is "high", while allowing a successively higher output at each successive stage of the input buffer circuit. The reference circuit 1 is compensated for power supply and process window variations.

Phase lock loop charge pump with symmetrical charge and discharge currents

Abstract: A charge pump in a phase lock loop equalizes the charge and discharge currents flowing into the filter capacitor independent of the loop node voltage for providing a linear VCO output frequency. The potential at the output of the charge pump determines whether the charging/discharging current is decreased or increased. An active up control signal to increase VCO output frequency and a low level potential at the output of the charge pump limits the charging current to the loop filter while increasing the discharge current. An active down control signal to decrease the VCO output frequency and a high potential at the output of the charge pump limits the discharging current while increasing the charge current. The voltage change at the output of the charge pump in response to the up control signal is made equal to the voltage change during the down control signal for providing equal charge and discharge currents to the loop filter independent of the loop voltage.