Institution
Codex Corporation
About: Codex Corporation is a based out in . It is known for research contribution in the topics: Signal & Network packet. The organization has 189 authors who have published 241 publications receiving 32205 citations.
Papers published on a yearly basis
Papers
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TL;DR: In the Letter, a partitioning algorithm is proposed that improves the performance of shell mapping, especially in the presence of severe nonlinear distortion.
Abstract: Shell mapping is a block coding method which can support fractional bits per symbol, while providing a shaping gain in a seamless manner. In the Letter we propose a partitioning algorithm that improves the performance of shell mapping, especially in the presence of severe nonlinear distortion.
1 citations
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13 Oct 1993TL;DR: In this article, the authors describe the findings of a recent study on quantization of the LPC parameters, represented as the arcsine of the reflection coefficients, using the structured vector quantizer (SVQ).
Abstract: This paper describes the findings of a recent study on quantization of the LPC parameters, represented as the arcsine of the reflection coefficients, using the structured Vector Quantizer (SVQ). Our results show that the SVQ can reduce the bit-rate by about 12 percent, compared to a conventional scalar quantizer. The SVQ also achieves a better performance than a split-VQ at a much lower implementation complexity.
1 citations
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23 Feb 19881 citations
01 Jan 1990
TL;DR: A custom VLSI architecture for implementing the CCITT G.722 64-kb/s (7-kHz) wideband audio coding standard is presented, capable of processing a full duplex channel in less than 625 cycles, which is 71-73% less cycles than are required by the reported general-purpose DSP implementations.
Abstract: A custom VLSI architecture for implementing the CCITT G.722 64-kb/s (7-kHz) wideband audio coding standard is presented. By tailoring the architecture to the algorithm, an architecture was designed that is capable of processing a full duplex channel in less than 625 cycles. That is 71-73% less cycles than are required by the reported general-purpose DSP implementations. In a 1.5- mu technology with a 100-ns cycle time, it is estimated that the architecture would consume 95000 mL/sup 2/ of silicon and support two full duplex channels on a single chip. The authors wrote a behavioral simulation of the architecture and its implicit microcode. This simulates the architecture's behavior at the bit level. The simulation passes the CCITT G.722 test vectors, demonstrating that the implementation conforms to the standard. >
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01 Apr 1986TL;DR: It is shown that it is possible to approximate true division by dividing a number by a power-of-two in the LS lattice algorithm that is based on the new direct-coefficient-update form of the exact least squares (LS) lattice algorithms.
Abstract: In this paper, we show that it is possible to approximate true division by dividing a number by a power-of-two in the LS lattice algorithm that is based on the new direct-coefficient-update form of the exact least squares (LS) lattice algorithm. The resulting pseudo-LS lattice algorithm is modestly slower in initial convergence than the true LS lattice algorithm, while it has a steady state error similar to the latter. The results are extended to a family of LS estimation algorithms covering a broader scope of applications.
Authors
Showing all 189 results
Name | H-index | Papers | Citations |
---|---|---|---|
Reinaldo A. Valenzuela | 56 | 265 | 26074 |
Gregory J. Pottie | 45 | 204 | 16464 |
Miriam Leeser | 29 | 195 | 2998 |
M.G. Hluchyj | 24 | 37 | 6090 |
G. David Forney | 17 | 40 | 1539 |
Kevin B. Theobald | 14 | 33 | 1421 |
Shahid U. H. Qureshi | 13 | 19 | 1496 |
Juin-Hwey Chen | 11 | 30 | 951 |
Jr. G.D. Forney | 10 | 11 | 8528 |
Fuyun Ling | 10 | 18 | 1076 |
Lanny L. Parker | 9 | 12 | 234 |
Arthur J. Barabell | 9 | 19 | 909 |
Ahmad H Atriss | 9 | 15 | 405 |
Pierre A. Humblet | 7 | 10 | 277 |
Vedat M. Eyuboglu | 7 | 8 | 535 |