Credence Systems

About: Credence Systems is a based out in . It is known for research contribution in the topics: Signal & Integrated circuit. The organization has 282 authors who have published 314 publications receiving 4857 citations.

Single photon avalanche diodes (SPADs) for 1.5 μm photon counting applications

Abstract: The paper reports on the design and characterization of InGaAs/InP single photon avalanche diodes (SPADs) for photon counting applications at wavelengths near 1.5 µm. It is shown how lower internal electric field amplitudes can lead to reduced dark count rates, but at the expense of degraded afterpulsing behaviour and larger timing jitter. Dark count rate behaviour provides evidence of thermally assisted tunnelling with an average thermal activation energy of ∼0.14 eV between 150 K and 220 K. Afterpulsing behaviour exhibits a structure-dependent afterpulsing activation energy, which quantifies how carrier de-trapping varies with temperature. SPAD performance simultaneously exhibits a dark count rate of 10 kHz at a detection efficiency of 20% with timing jitter of 100 ps at 200 K, and with appropriate performance tradeoffs, we demonstrate a 200 K dark count rate as low as 3 kHz, a detection efficiency as high as 45%, and a timing jitter as low as 30 ps.

Graphical data base editor

Abstract: A system manipulates stimulus/response signal data associated with an integrated circuit design, such as from a computer-aided engineering simulator, and converts the data into a format acceptable by a tester device which tests a prototype or production integrated circuit. The data is graphically displayed as a waveform and as a vector sequence. On-screen editing of either display is reflected in the other display. Further, the same displays are used to convert the data from event-based data into cycle-based template data compatible with a tester. A mix between event and state data during the conversion is allowed. A standard frame generation language is presented for defining tester frames for each signal within a template or timeset. A workbench editor provides for icon-based control of the system.

Modular integrated circuit tester with distributed synchronization and control

Abstract: A modular integrated circuit tester (10) includes a set of tester modules (14) for carrying out a sequence of tests on an integrated circuit device under test (DUT) (12). Each module includes a memory (54) for storing instruction sets indicating how the module is to be confugured for each test of the sequence. Before the start of each test, a microcontroller (30) in each module executes an instruction set to appropriately configure the module for the test. The microcontroller in each module thereafter sends a ready signal to a start logic circuit (20) in each other module indicating that it is ready to perform the test. When microcontroller of all modules taking part in the test have signaled they are ready, the start logic circuit in each module signals its microcontroller to begin the test. The molules then carry out the test with their activities synchronized to a master clock signal. The process of configuring the modules, generating the ready signals and commencing a test is repeated for each test of the sequence.

Compensated delay locked loop timing vernier

Abstract: A timing vernier (10) produces a set of timing signals (T1-TN) of similar frequency and evenly distributed in phase by passing an input reference clock signal (CLK) through a succession of delay stages (S1-SN), each stage providing a similar signal delay. A separate one of the timing signals is produced at the output of each delay stage. The reference clock signal and timing signal output of the last delay stage are supplied as inputs to a phase lock controller (14) through separate adjustable first (16) and second (18) delay circuits. The phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. In accordance with the invention, the delays of the first and second delay circuits are adjusted (20) to compensate for controller phase lock error.

Partitionable embedded circuit test system for integrated circuit

Abstract: A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.