Showing papers by "Freescale Semiconductor published in 1987"

Wait mode power reduction system and method for data processor

Abstract: A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.

Sloped contact etch process

Abstract: The process described provides a sloped contact etch The process has the steps of: etching a substrate 12 then removing the polymer that is produced during the substrate 12 etch These two steps are alternated until a desired depth is reached Next, the resist 11 is etched followed by an etch of the substrate 12 This is then repeated until the required depth is reached By varying the duration and repetition of the etches, the slope of the etch can be regulated

Means for stabilizing polycrystalline semiconductor layers

Abstract: Implantation of oxygen or nitrogen in polysilicon layers to a dose above about 10 15 ions/cm 2 retards rapid grain boundary migration of conventional dopants such as B, P, As, Sb, and the like during dopant activation. Pre-annealing of the poly films to increase the grain size also decreases rapid grain boundary migration. The effects can be combined by first pre-annealing and then implanting oxygen or nitrogen before introducing the dopant. It is desirable to anneal the oxygen implant before introducing the dopant to allow for oxygen diffusion to the grain surfaces where it precipitates and blocks the grain boundaries. Vertical and lateral migration of the dopants can be inhibited by placing the implanted oxygen or nitrogen between the dopant and the location desired to be kept comparatively free of dopants. When very high dopant activation temperatures are used the blocking effect of the oxygen on the grain boundaries is overwhelmed by dopant diffusion through the grains.

EPROM device using asymmetrical transistor characteristics

Abstract: An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

Intelligent electrically erasable, programmable read-only memory with improved read latency

Abstract: An intelligent electrically erasable, programmable read-only memory achieves improved worst-case read operation latency by allowing for the interruption of write operations by subsequently received read requests. In the preferred embodiment, a state machine controller executes write operations by an iterative process of write pulses and write verify cycles. In addition, cells are erased prior to being written to by a similar iterative process. Both the write operations and the erase operations may be interrupted by read requests received after the write operation has begun execution. To avoid reading incorrect data in the case of a read operation at the same address as an interrupted write operation, a comparator matches read operation addresses with latched write operation addresses and provides the read operation data from a write data latch in the case of a match.

Tab-type semiconductor process

Abstract: A TAB (Tape Automated Bonding) process uses single-layer tapes to form a semiconductor structure. Beam leads on a metal tape are "inner-lead bonded" to a chip. Each chip site on a specially-formed plastic tape has a central portion and a peripheral portion which are bonded to the chip so that the central portion forms a protective cover over the chip and the peripheral portion acts as a support for the beam leads during probe testing, excising and forming operations, etc. The bottom surface of the chip preferably remains uncovered so that it can, if appropriate, be electrically connected to ground or another potential.

Modified source/drain implants in a double-poly non-volatile memory process

Abstract: Implementing modified souce/drain implants in a non-volatile memory process while leaving the source/drain regions in the memory cells of the device unmodified and adding no critical mask steps. Methods for implementing both low dose drain and graded source/drain modifications in a double poly non-volatile memory process include the possibility of leaving the spacers used to modify the peripheral source/drain regions in place in the array portion of the device. Alternate methods include the possibility of removing the spacers in the array portion without the addition of critical mask steps and of keeping the spacers out of the array portion entirely.

Trench cell for a dram

Abstract: A DRAM memory cell has a trench capacitor and a transistor. The trench of the trench capacitor penetrates to a buried layer which acts as the primary portion of one of the plates of the capacitor. When the buried layer is the same conductivity type as the transistor of the memory cell, the buried layer is biased to a voltage selected to reduce the maximum voltage across the capacitor. This allows for a reduction in the thickness of the dielectric which coats the trench which increases the capacitance of the capacitor. When the buried layer is of the opposite conductivity type from the transistor type of the memory cell, there is no parasitic MOS transistor formed between the primary portion of the capacitor plate and the source of the transistor of the memory cell.

Forming a trench capacitor

Abstract: A trench capacitor having increased capacitance. By means of the oxidation enhanced diffusion (OED) effect, locally outdiffused regions in the doped substrate of a semiconductor material may be formed. Thus, greater capacitance can be achieved for a trench capacitor of equal depth. This technique avoids the heretofore required extra doping in the well of opposite conductivity type that would have been necessary to prevent punchthrough if the entire lower, heavily doped region or substrate had to be formed closer to the surface of the overlying lightly doped semiconductor layer. The locally outdiffused regions may be accomplished by standard oxidation techniques.

Poly-sidewall contact transistors

Abstract: Improved semiconductor devices having minimum parasitic junction area are formed by using multiple buried polycrystalline conductor layers to make lateral contact to one or more pillar-shaped epitaxial single crystal device regions. The lateral poly contacts are isolated from each other and from the substrate and have at least one polycrystalline pillar extending to upper surface of the device to permit external connections to the lowest poly layer. The lateral epi-poly sidewall contacts are recessed under the intervening oxide layers to separate them from the active device regions in the center of the epi pillar. The structure is made by depositing three dielectric layers with two poly layers sandwiched in between. Holes are anisotropically etched to the lowest poly layer and the substrate. The exposed edges of the poly layers are oxidized. These edge oxide regions are removed in the holes where the device pillars are epitaxially grown. The remaining edge oxide regions isolate the buried conductor layers, contacts, and isolation walls. The polycrystalline pillar extending from the lowest poly layer to the device surface is formed at the same time as the epi-pillar. The structure is self-aligned and self-registering.

Trench isolation method for semiconductor devices

Abstract: A method is described for forming dielectric filled isolation trenches in semiconductor substrates in which a differentially etchable etch-stop layer is provided above the surface of the substrate during the trench filling process so that the height of the trench filling relative to the surface of the substrate may be adjusted for optimum overall results during subsequent fabrication steps and so that the substrate surface may be protected from contact with the etching reagents used during planarization of the trench filling material. This avoids damage to the substrate surface and permits improved surface planarity.

Semiconductor protection circuit having both positive and negative high voltage protection

Abstract: An input protection circuit is provided which prevents positive and negative voltages significantly higher than a supply voltage potential from damaging operational circuitry connected to an input terminal. A bipolar transistor has current conducting electrodes connected between the supply voltage and the input terminal. A first MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and collector of the bipolar transistor in response to the sign and magnitude of an input signal. A second MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and emitter of the bipolar transistor in responses to the sign and magnitude of the input signal.

Method and apparatus for selectively evaluating an effective address for a coprocessor

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Latch-up control for a CMOS memory with a pumped well

Abstract: A CMOS DRAM has an array in a well which is pumped to a voltage greater than the power supply voltage. The transfer devices of the memory cells in the array are of a conductivity type opposite to that of the well. The transfer devices each have a source/drain of the opposite conductivity type to that of the well which is connected to a bit line. The bit line will tend to rise in voltage at power-up which has the potential of forward biasing the PN junction between the source/drain and the well. The bit line rise is due to a word-line rise the rate of which is controlled so that the bit line rise does not exceed the rise in array voltage. The bit lines are ensured of being separated in voltage at the beginning of the first active cycle by enabling the N channel portion of the sense amplifier during power-up. The P channel portion of the sense amplifier is disabled during power-up to avoid too rapid of a rise in voltage on the bit lines. Equalization of the bit lines is suppressed during the first cycle to avoid having the sense amplifier face the high current drain condition of little or no voltage differential at low voltage.

Phase locked loop having a filter with controlled variable bandwidth

Abstract: A phase locked loop (PLL) is provided having a filter with a programmable wide and narrow bandwith. When PLL circuit operation is initiated or when the operational frequency of the PLL is changed by a substantial amount, a phase detector functions to force the filter in a wide bandwith mode to allow fast circuit operation in the transient mode. After the PLL output has settled close to a predetermined frequency, the number of times the output frequency varies above and below the predetermined frequency before reaching a locked state is detected and counted. After the output frequency has varied above and below the predetermined frequency a predetermined number of times, the filter is automatically switched to a low bandwith mode to allow the PLL to operate in a stable manner.

Micron and submicron patterning without using a lithographic mask having submicron dimensions

Abstract: An electronic process is provided for creating a small dimensioned pattern in a semiconductor device. In one embodiment, the pattern functions to electrically separate two areas of the substrate by less than a micron. A lithographic mask which does not have to utilize dimensions as small as those being formed on the semiconductor device is used to form a predetermined pattern with at least one separation region by irradiating and developing a photoresist material. A layer of buffer material below the photoresist material reacts with a reactive ion etch to form a separation area with sloping sides comprised of polymer filaments produced from the reaction. The sloped sides of the separation region provide a separation dimension in the substrate of the semiconductor structure which is significantly smaller than a corresponding dimension required to be implemented on the lithographic mask.

Programmable delay circuit

Abstract: A monolithically integrated delay circuit is provided that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to said gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital output signal that is delayed with respect to the digital input signal.

Method of forming edge-sealed multi-layer structure while protecting adjacent region by screen oxide layer

Abstract: A process for forming a DRAM cell having a capacitor adjacent a field effect transistor (FET), wherein the FET fabrication area is protected from adverse effects of the capacitor formation. The process is misalignment tolerant and provides FETs with appreciably lower defects in the substrate beneath the FET. Additionally, the process eliminates the need to stop an etching operation on a thin capacitor dielectric layer.

Method and apparatus for selectively delaying an interrupt of a coprocessor

Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Semiconductor memory with divided word lines and shared sense amplifiers

Abstract: A semiconductor memory device having a divided word line architecture in which each block of the memory array is divided into half-blocks and the half-blocks of each block are located on different halves of the device separated by the row decoder. A data line bussing scheme cooperates with this unique organization of the memory array to provide for sense amplifier sharing. This feature allows fewer, and larger sense amplifiers for better performance.

Polysilicon pattern for a floating gate memory

Abstract: An integrated circuit floating gate memory is formed using two layers of polysilicon. The first layer of polysilicon is patterned twice, once before the second polysilicon layer is deposited, and again as part of the etch of the second layer of polysilicon. Stringers of the second layer of polysilicon can form along the edge of the first etch of the first layer of polysilicon. The first etch of the first layer of polysilicon is patterned so that even if these stringers are subsequently formed, there is no harm.

Plastic carrier tape having lowered cross rails

Abstract: A plastic carrier tape for electronic components and the like having cross rails at a predetermined distance below taping rails thereby allowing for a more uniform adhesion of a tape cover to the plastic carrier tape. This more uniform adhesion will allow for a uniform pull force to remove a tape cover thereby enabling the plastic carrier tape to be more easily used in an automated production line.

Double-implant process for forming graded source/drain regions

Abstract: A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.

Signature circuit responsive to an input signal

Abstract: An integrated circuit has a signature circuit which provides information concerning the integrated circuit itself. This information can, for example, specify that redundancy has or has not been implemented. Other potential information can relate to the particular mask set, the speed of the integrated circuit, and/or the manufacturer. The information is provided on a normal output terminal of the integrated circuit. A load is selectively coupled to the output terminal in response to an input signal of the integrated circuit if a particular node is programmed to a first logic state. If the particular node is programmed to a second logic state, the load is not responsive to the input signal. A load variation then indicates one condition of the integrated circuit, and no load variation indicates another condition. Numerous outputs can be similarly used to provide additional amounts of information according to some selected code.

Superlattice gate field effect transistor

Abstract: A quasi 1-dimensional electron gas transistor has been provided having a source electrode and a drain electrode. A plurality of electrodes are positioned between the source and drain electrodes in a manner which are parallel to the electron flow between the source and the drain electrodes. In one embodiment, the electrodes are interconnected by a gate electrode while in an alternate embodiment all the electrodes are connected to the source electrode and insulated from the gate electrode. This device provides a quantum wire for quasi 1-dimensional electron flow.

Dynamic disable mechanism for a memory management unit

Abstract: In a data processing system comprising a central processing unit (CPU), a memory management unit (MMU) and a storage system, the MMU translates each of the logical addresses output by the CPU to a corresponding physical address in the storage system by selectively using translation descriptors stored in an address translation cache. In response to receiving a dynamic disable signal, the MMU will provide each logical address as the corresponding physical address without translation. In addition, the MMU will preserve the state of the entries in the address translation cache, and "freeze" the translation activities.

Single tub transistor means and method

Abstract: A means and method for forming a single tub transistor, such as for example a vertical NPN bipolar transistor surrounded by an isolation wall, is described. Multiple polysilicon and dielectric layers are employed in conjunction with a master mask and with isotropic and anisotropic etching procedures to define the contacts and active regions of the device without resorting to precision alignments. Sub-micron lateral device contacts are easily achieved even with comparatively coarse lithographic methods through use of sidewall spacers for controlled narrowing of critical device openings. The finished device is especially compact, has low resistance contacts for its size, and provides very high speed operation.

Process for developing implanted buried layer and/or key locators

Abstract: The present invention consists of a process of blanket implanting a key area and buried layer without the use of nitride or thick oxide layers. The key area is then etched leaving the surface of the key area below the surface of the buried layer. Upon growing an epitaxial layer, the key area will be identifiable by a step in the surface of the epi layer.

Memory input buffer with hysteresis and dc margin

Abstract: A memory has input buffer circuit which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer circuit includes a pair of input NOR gates which provides for independent signal paths to a cross-coupled latch. Independent hysteresis circuits are provided to each signal path between the two NOR gates and the cross-coupled latch. This allows for independently selecting the amount of dc margin and hysteresis so that the use of hysteresis does not adversely effect dc margin.

Photon recycling light emitting diode

Abstract: A photon recycling light emitting diode consisting of a stack of direct bandgap semiconductor active layers on a substrate with increasing bandgap energy from the substrate, separated by barrier layers having higher bandgap energy and capped with a window layer having a bandgap energy higher than the active layers.