Showing papers by "Freescale Semiconductor published in 1988"

Redundancy for a block-architecture memory

Abstract: A block architecture memory has two stacks of memory blocks. Between the two stacks are blocks of sense amplifiers. Each block of sense amplifiers is coupled to a memory block in each of the stacks of memory blocks via local data lines. Located at the bottom of each stack of memory blocks is a redundant block of columns of memory cells. There is a redundant sense amplifier located between and coupled to the redundant blocks of columns via local data lines. The redundant sense amplifier is also coupled to a redundant global data line. An input/output multiplexer is coupled to all of the global data lines. The multiplexer provides and receives external data. If one of the redundant columns is to replace a defective column for a particular address, then the redundant global data line carries data which corresponds to the external data.

Paged memory management unit which evaluates access permissions when creating translator

Abstract: A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator. In general, the PMMU includes: a cache having a plurality of storage locations for storing the translators, each of the storage locations including a write protect indicator and a read protect indicator adapted to be selectively set; translation control logic for storing an assembled translator in a selected one of the storage locations, the translation control logic setting the write protect indicator of the one storage location in response to a write protect signal associated with the descriptor used to assemble the translator and the read protect indicator of the one storage location in response to a read protect signal associated with that descriptor; and access control logic for preventing the translator from being used to translate the logical address in support of a write operation if the write protect indicator of the one storage location is set or in support of a read operation if the read protect indicator of the one storage location is set. In the preferred form, the logical address has an access privilege level associated therewith and the descriptor includes a selected write access privilege level and a selected read access privilege level, the translation control logic setting the write protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the write access privilege level and the read protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the read access privilege level.

Voltage clamped differential to single ended converter circuit

Abstract: A MOS differential to single ended converter circuit is provided for supplying a single ouput signal in response to first and second differentially related current being supplied to first and second junctions thereof. The converter circuit includes first and second MOS transistors each having gate, drain and source electrodes with the gate electrodes being coupled together while the drain and gate electrodes of the first transistor are interconnected. The drain and source electrodes of the pair of transistors are respectively coupled in series with the first and second junctions. First and second bipolar transistors each having first, second and control electrodes are provided for limiting the voltage swing at the drain of the second MOS transistor. The contol and first electrodes of the first bipolar transistor are coupled respectively to the first and second junctions whiled the control and first electrodes of the second bipolar transistor are respectively coupled to the second and first junctions with the second electrodes of the two bipolar transistors being coupled to an additional common terminal.

Low power output driver circuit with slew rate limiting

Abstract: A slew rate limited output driver circuit has an output terminal which varies between two power supply voltage levels in response to an input data signal. The output signal is slew rate limited by a capacitor. In order to prevent a full range of the output voltage from being placed across the capacitor, the voltage across the capacitor is limited to only one-half the full range by forcing one electrode of the capacitor to remain at a voltage potential equal to a reference voltage which, in one form, is substantially halfway between the two power supply voltages.

Latching sense amplifier

Abstract: A sense amplifier for fast and reliable sensing of a small voltage differential is accomplished by the integration of a latch which uses regenerative feedback. Complementary devices are used within the sense amplifier to modify its configuration from an amplifier to a latch. The integration of the latch for gain allows the use of a single-ended sense amplifier section, as opposed to requiring a double-ended design for level shifting and symmetrical sensing of `0` and `1`. The output is a pair of full-rail complementary signals that can be directly used by standard CMOS logic downstream.

Process for preferentially etching polycrystalline silicon

Abstract: This disclosure relates to a process for etching polycrystalline silicon in preference to single crystal silicon. Polycrystalline silicon is anisotropically etched in a plasma which inclues a noncarbonaceus silicon etching compound such as chlorine together with about 0.4-1.5 percent by volume of oxygen. The process is used to fabricate semiconductor devices which require the etching of polycrystalline silicon in the presence of exposed monocrystalline silicon.

Microprocessor having high current drive

Abstract: An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

Method and apparatus for a data processor to support multi-mode, multi-precision integer arithmetic

Abstract: In a data processor having an integer arithmetic unit, the carry-in control logic, carry-out control logic, and the overflow control logic of the arithmetic unit are adapted to be directly controlled by respective carry-in enable, carry-out enable, and overflow enable fields of the integer arithmetic instructions during the execution thereof.

Clock distribution circuit having minimal skew

Abstract: A clock distribution circuit for distributing a clock signal to a plurality of other circuits, having a substantially reduced skew between the input signal and the plurality of output signals wherein signals are transmitted from an input gate to a plurality of output gates and output pads along radially disposed metalization lines. The radially disposed metalization lines are terminated at forty five degrees, thereby reducing reflections, and are of equal length for like signals.

Vacuum assisted transfer mold and vent pin

Abstract: The mold described has walls disposed about the mold plates and vent pin retainer plates to permit a vacuum to be generated. The vent pins have been designed to be self cleaning. A pin having a generally cylindrical shape is used. A first portion of the pin has a face defined by a chord of the cylinder. The face leaves a small space between the pin and the opening wall which permits the atmosphere to be removed from the cavity. Below the first portion is a second portion, smaller in diameter than the first portion. Below the second portion is a third portion of essentially the same design as the first portion rotated 45°. This portion cleans the walls of the opening when the pin is raised to eject the parts.

Testing arrangement for a DRAM with redundancy

Abstract: A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.

Method and apparatus for handling out of order exceptions in a pipelined data unit

Abstract: A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.

Method of forming semiconductor structure isolation regions

Abstract: A planarized dielectric isolation region for semiconductor devices and integrated circuits is created by providing a semiconductor substrate, providing on the substrate an oxide/nitride mask with an opening for defining the isolation region and a closed portion for defining the desired semiconductor islands, anisotropically etching a trench into the semiconductor substrate, isotropically etching the substrate so as to slightly undercut the oxide/nitride mask, thermally oxidizing the substrate to form a thin oxide layer on the bottom and sidewall of the trench wherein the outer surface of the thermal oxide approximately lines up with the edge of the oxide/nitride mask at the top of the trench sidewall, filling the trench with a conformal deposited material (preferably a dielectric), providing a mask over the conformal material which is the complement to the trench etch or island mask but of smaller lateral dimensions so as to cover those portions of the conformal layer which do not rise up over the semiconductor island, etching away the exposed portions of the conformal material to a level approximately co-planar with the island surface and the portion of the conformal material under the mask, and removing the mask.

Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit

Abstract: A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.

Method of eliminating bird's beaks when forming field oxide without nitride mask

Abstract: A method of selectively forming a field oxide in a semiconductor device is provided by implanting a dopant into selected regions of a semiconductor substrate. A high concentration of dopant provides for an enhanced oxide growth rate. Another dopant may be implanted if necessary to provide a high field threshold voltage to prevent inversion. Annealing the semiconductor substrate and growing the oxide at a predetermined temperature will keep the high concentration of dopant in the semiconductor substrate, and thus maintain a state of enhanced oxide growth throughout the oxidation cycle. By taking advantage of enhanced oxidation, a mask, such as silicon nitride, is not required to prevent the substantial growth of oxide in the undoped region or active area.

Integrated gyrator oscillator

Abstract: An oscillator is disclosed comprising a pair of gm stages wherein the output of the second gm stage is coupled to the inverting input of the first stage and the output of the latter is coupled to the non-inverting input of the former; first and second capacitors coupled respectively between the outputs of the two gm stages and ground and feedback circuitry coupled between the output of the first gm stage and the non-inverting input of thereof while the inverting input of the second gm stage being coupled to ground. Because the first gm stage is operated as a negative gm, this stage simulates an inductor using the first capacitor that is coupled to the output of the stage.

Substrate mounting assembly

Abstract: In a substrate mounting assembly (10) critical bonding pads (20) adjacent one lateral edge (21) of a ceramic substrate (11) are connected to semiconductor die (13) via wires (26). The substrate and die are mounted on a aluminum base carrier plate (12) which serves as a heat sink for the semiconductor die. A relatively rigid first adhesive (40) is applied in one area between the substrate and base carrier so as to effectively fix one lateral edge (21) of the substrate and the critical bonding pads (20) with respect to the base carrier, while a second adhesive (41), comprising an acrylic adhesive tape, bonds other areas of the ceramic substrate to the base carrier. At a lateral edge (23) of the substrate opposite to the lateral edge (21) adjacent the critical bonding pads, additional bonding pads (22) are provided and wires/conductors (27) connect these additional bonding pads to lead frame projections (28) from a non-conductive housing (29) fixed to the aluminum base carrier. This configuration insures sufficient mechanical support for the ceramic substrate while also providing minimal stress for the wires connecting the semiconductor die to the critical bonding pads.

Monolithic microwave integrated circuit having vertically stacked components

Abstract: A monolithic microwave integrated circuit having multiple, vetically stacked components wherein at least three metal layers isolated from each other by layers of non-conducting material are formed on a semi-insulating substrate, generally comprised of gallium arsenide. Vertically stacked capacitors, inductors and various combinations thereof may be fabricated using the present invention. Further, the vetrically stacked components may be formed on active devices such as FETs and diodies.

Multi-rate cascaded noise shaping modulator

Abstract: A noise shaping modulator for use in sigma delta modulation data conversion has two or more cascaded quantization loops. A first quantization loop is operated at a first sampling frequency and one or more higher order quantization loops are operated at a second sampling frequency. Due to speed limitations of analog circuitry in the first quantization loop, a significant improvement in signal to noise ratio may be achieved in a sigma delta modulation data converter by selecting the second sampling frequency higher than the first sampling frequency.

Cache tag comparator with read mode and compare mode

Abstract: A cache TAG, which has a compare mode, an and/or/invert mode, and a read mode, has a programmable comparator which receives an external data signal and an output from an array of memory cells and provides an output to a secondary amplifier. The secondary amplifier provides an output to a match comparator in the compare mode and the and/or/invert mode and to an output buffer in the read mode. The programmable comparator is programmable according to the mode of the cache TAG. The compartor uses selectively enabled transmission gates which provide minimal delay in providing the appropriate data to the secondary sense amplifiers.

Data device module having locking groove

Abstract: A module is described for use in data devices such as smart cards. The module consists of a contact carrier having contacts, an integrated circuit, and a base enclosing the integrated circuit. The base is formed to provide a groove around the perimeter such that when the device is formed, material from an intermediate layer will flow into the groove and secure the module to the card.

Coplanar die to substrate bond method

Abstract: A coplanar die to substrate bond method wherein a plurality of die (14) are aligned on a silicon wafer substrate (10) in a predetermined relationship and a slurry of glass (24) is applied to bond them together. This occurs while either on a flat (20) or a grooved plate (22). When the silicon wafer substrate (10) and the plurality of die (14) are ready for firing, they are placed on a grooved plate (22) so that grooves (26) are below the glass (24) thereby decreasing the capillary force which commonly causes overflow. With reduced overflow, the bonding can be done at a higher temperature to reduce underflow. Because there is no underflow or overflow using this process, a greater degree of coplanarity is achieved thereby making future processing steps, such as the processing of interconnect lines, much easier to perform.

Selective metal deposition process

Abstract: A method for the selective deposition of metals in semiconductor device manufacturing wherein a wafer surface is subjected to a hydrogen species that reduces oxidation on conducting materials while also removing impurities from non-conducting materials. Metals are then selectively deposited upon the conducting materials and not upon the non-conducting materials. It should be understood that the hydrogen treatment step and the selective metal deposition step may be performed simultaneously or by using two separate processing steps.

Output compare system and method for a data processor

Abstract: A data processor and method includes a timer system for producing a first output compare signal when a counter value equals a compare value. A register alternatively produces a second output compare signal in response to having a given bit value written therein. Logic circuitry provides an output compare function in response to either the first or the second output compare signals.

Superconducting thick film

Abstract: An Yttrium Barium Copper Oxide-based thick-film paste (12) is disclosed, which when deposited on an alumina substrate (10) is superconducting above the temperature of liquid nitrogen and substantially free of mechanical defects such as cracking or peeling. A method of applying the paste, including the curing process, insures that the YBC superconductor (12) is bonded to the substrate (10).

Multichip IC module having coplanar dice and substrate

Abstract: A multichip IC module having dice and substrates coplanarly bonded therein. After the dice are aligned into die openings of the substrate, a glass slurry is applied and the module is fired to solidify the glass. Because of shrinkage of the glass slurry firing, a groove results between the dice and the substrate. To fill on this groove, a polyimide or like film is adhered and then pressued and cured on the surface of the dice and substrate. This film is used as a base for interconnect lines.

Apparatus and method for testing semiconductor devices

Abstract: A signal of a known period is transmitted through a semiconductor device to the set input of a flip-flop. The reset input of the flip-flop receives the original signal delayed by one-half the known period. The inverted and noninverted outputs of the flip-flop are then filtered and input to a leveling circuit and a differential amplifier. The leveling circuit adjusts the outputs of the flip-flop to produce signals of constant known amplitude. The output of the differential amplifier represents the delay of the signal through the semiconductor device.

Semiconductor die for plastic encapsulation having an adhesion promoter

Abstract: A semiconductor die for plastic encapsulation having an adhesion promoter selectively disposed on an outer surface enabling better adhesion between the semiconductor die and a plastic encapsulation. The improved adhesion allows for less relative motion between the semiconductor die and the plastic encapsulation. The reduction of relative motion significantly decreases the delamination progression throughout the semiconductor device and allows for an increased semiconductor device lifetime.

Multifunction onboard input/output termination

Abstract: An onboard structure used to terminate standard ECL devices of non-gate array devices which save space on the multichip module by requiring only non-discrete components. These non-discrete components include a first transistor having its collector coupled to the emitter of a second transistor, and its based coupled to the collector of a third transistor. Different variations of the onboard structure permit the structure to be a 50 ohm output, a 25 ohm output, a 60 ohm output, a series terminated output or a current sourced input termination.

Shock proof steering module assembly

Abstract: A steering module assembly having a contoured housing unit to receive a PC board which has soldered to it a plurality of optoelectronic devices wherein neither said plurality of optoelectronic devices nor said PC board come in direct contact with the housing unit. The PC board also has a saddle element which contains snap retainers to receive each of said plurality of optoelectronic devices. A fitted cover encloses the housing unit.