Showing papers by "Freescale Semiconductor published in 1989"

High performance overmolded electronic package

Abstract: A package for containing high performance electronic components, such as high speed integrated circuits (ICs). The package bears a substrate of multiple layers having a cavity therein. Leads may be placed within holes in the substrate and soldered or otherwise electrically connected to conductive patterns or layers in the substrate. A thermally conductive insert is attached to one side of the substate. The insert has a pedestal which protrudes through the cavity in the substrate. An electronic component, such as an IC may then be mounted on the pedestal and electrically connected to a conductive metal pattern on one of the layers of the substrate. This assembly may then be coated with a dielectric material to form the package body, leaving the distal ends of the leads and the back side of the insert exposed. Since the IC chip or other component is directly mounted on the insert, waste heat generated by the chip may be directly channeled outside the package through the insert which effectively forms one wall of the package. The exposed leads may be formed into the desired configuration, including shapes suitable for surface mount technology. The use of a multiple layer substate permits the inclusion of ground and power planes for high performance circuits, such as emitter coupled logic (ECL) gate arrays, within the package itself.

No-chip debug peripheral which uses externally provided instructions to control a core processing unit

Abstract: A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.

Fabrication of pad array carriers from a universal interconnect structure

Abstract: A method of manufacturing a chip carrier from a universal ceramic substrate provides for a universal ceramic substrate having first and second opposed sides and an array of conductively filled through-holes. On the first side, wire bond pads and conductors connected to the conductively filled through-holes are provided as required. Similarly, on the second side, solder pads on the conductively filled through-holes are provided as required. Finally, at least one insulating layer is provided over part of the first side for die attachment.

Multiple step metallization process

Abstract: Metal step coverage is improved by utilizing a multiple step metallization process. In the first step, a thick portion of a metal layer is deposited on a semiconductor wafer at a cold temperature. The remaining amount of metal is deposited in a second step as the temperature is ramped up to allow for reflow of the metal layer through grain growth, recrystallization and bulk diffusion. The thick portion of the metal layer deposited at the cold temperature is of adequate thickness so that it remains continuous at the higher temperature and enhances via filling.

Method for assembling, testing, and packaging integrated circuits

Abstract: An assembly flow in which integrated circuits are burned-in and parametrically tested before assembly is provided. The integrated circuits are sorted based on the results of the parametric testing, and assembled in groups with similar parameters. Integrated circuits from a single group are assembled on a leadframe and encapsulated, marked, and tested again while still attached to the leadframe. Finally, the packaged integrated circuits are separated from the leadframe and those meeting predetermined parameters are loaded into carrier sleeves.

Method of fabricating airbridge metal interconnects

Abstract: An improved method of fabricating airbridge metal interconnects uses two photoresist layers having different solubility characteristics. This allows for the removal of one resist without affecting the other. Thus, the underlying semiconductor structure is protected from subsequent etches of the ground plane metal. Consequently, a greater process latitude allows for obtaining higher device yields in fabricating high frequency semiconductor devices employing airbridge metal interconnects.

Digital phase lock clock generator without local oscillator

Abstract: A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two phase generator which in turn feeds back to the PD for comparison with the reference clock. This process is repeated until phase locking is obtained.

Integrated circuit with clock generator

Abstract: A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.

Process for making a multilayer metallization structure

Abstract: A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer is formed over a bottom interconnect layer, and an interlayer dielectric is formed on the sacrificial layer. A via is etched in the interlayer dielectric, exposing the sacrificial layer. The sacrificial layer is isotropically etched to expose an area of the interconnect metal that is larger than the area of the via and a via metallization is selectively formed on the interconnect metal by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer, is filled with the via metallization, thereby providing a contact area to the bottom interconnect metal which is larger than the via metallization itself.

Integrated circuit microprocessor with programmable chip select logic

Abstract: An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.

Integrated Schottky diode and transistor

Abstract: An improved means and method is described for forming a Schottky diode integrated with transistors and other devices which is particularly useful where both control circuits and a large power device are on the same chip. Nested N- (6), P- (8), N- (14) and P+ (26-30) regions are formed on an N+ semiconductor substrate (5). A portion (45H) of the overlying dielectric (45) is removed adjacent one of the P+ regions (28, 29) over the N- region (14) and a Schottky contact (54C) formed to the N- region (14) and an ohmic contact to the adjacent P+ region (28-29). N+ (34, 36) and P+ (26, 30) regions are desirably provided where the junctions between the N-(14) /P-(8) regions and the P-(8) /N-(6) regions intersect the surface to provide contact to the N-(14) and P- (8) regions respectively. A P region (41) extends through the upper N- region (14) and has U-shaped arms (76) which partially overlie an annular shaped P+ region (28-29) and is located between the active region of the PNP transistor (27, 14, 8) and the collector contact (54A, 54E) to serve as a Kelvin probe. The arrangement is particularly valuable where a vertical PNP device (27, 14, 8) without a buried collector region is required.

Contact structure and method

Abstract: A semiconductor device structure including a contact and a method for its fabrication are disclosed. In accordance with one embodiment of the disclosure, a contact is formed between a monocrystalline silicon substrate and an overlying silicon layer. A silicon substrate is provided which has a first insulating layer formed thereon. A layer of silicon is deposited and patterned over the insulator layer. The patterned silicon layer is then oxidized and a contact opening is etched through the first insulator layer and the silicon dioxide is expose portions of the silicon substrate and an adjacent portion of the patterned silicon layer. A further layer of polycrystalline silicon is then selectively deposited onto the exposed portions of the substrate and silicon layer to form an electrical connection between the two.

Multifunction ground plane

Abstract: A multifunction ground plane for an electrical device such as an integrated circuit (11) is provided by a plurality of conductors (14) each having one end thereof adapted to be coupled to the electrical device (11) with a ground plane (20) adjacent and electrically isolated (16) from said plurality of conductors (14). The ground plane (20) includes a plurality of electrically isolated portions (21) each of which can be coupled to the electrical device (11) to provide operating potential (V) and/or signals thereto or therefrom. The isolated ground plane portions (21) have an impedance less than that of the electrical conductors (14) and provide an alternate means for connecting operating potential(s) (V) and/or operating signals to and from the electrical device (11) while still functioning as a ground plane for the electrical conductors (14).

Integrated circuit structures having polycrystalline electrode contacts

Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

Variable length shifter for performing multiple shift and select functions

Abstract: A variable length shifter for performing multiple shift and select functions. The shifter has a number of cells equal to an operand length, ordered from a most significant to a least significant, or leftmost to rightmost. Each cell stores a bit of the operand, and is coupled to each adjacent cell and to a cell four bits adjacent in either direction, if any. In addition, each cell is coupled to a return bus for implementation of boundary conditions associated with the operation. Besides being expandable to an arbitrary size operand, the shifter implements a register select function using primarily existing circuitry.

Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation

Abstract: A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.

Bandgap reference circuit with improved output reference voltage

Abstract: A bandgap reference circuit providing a continuous output reference voltage. The bandgap reference circuit comprises an operational amplifier, an output circuit, and a compensation circuit. The operational amplifier receives a first input signal and a second input signal and provides an output signal in response to a difference in voltage between the first input signal and the second input signal. The output circuit receives the output of the operational amplifier and provides an output reference voltage. The output circuit provides the first input signal and the second input signal to the operational amplifier in such a way as to maintain the output reference voltage at a substantially constant value. The compensation circuit provides a current to the output circuit to compensate for currents conducted from the bases of transistors in an input stage of the operational amplifier, thereby making the output reference voltage more stable.

Grounding an ultra high density pad array chip carrier

Abstract: A die pad (108) with a punched hole providing a throughway (110) is affixed upon the chip carrier base 100. Such throughway permits the electronic interconnection of the die backside (112) to a conductive runner (104) by electrically conductive material (110) set between the die backside (112) and the conductive runner (104).

Method of reducing defects on semiconductor wafers

Abstract: A reduction in the number of impurities and defects on a semiconductor wafer is provided by cleaning the wafer in a hydrochloric acid, hydrofluoric acid, and water solution. This HCl:HF:H2 O solution removes silicon dioxide as well as metallic impurities from the wafer surface, thus preventing the formation of defects on the wafer and increasing the quality and yield of semiconductor devices.

Semiconductor pressure sensor means and method

Abstract: A piezo-resistive pressure sensor element is formed in the front face of a silicon wafer. A thin diaphragm is formed under the sensing element by anisotropically etching a cavity from the rear face of the wafer. The rear face (cavity-side) rupture pressure of the silicon diaphragm is at least doubled by subjecting the anisotropically etched cavity to a mild isotropic etch. This substantially improves the cavity-side over-pressure rating of the finished pressure sensor without any significant change in the device sensitivity or allows higher sensitivity to be obtained for the same over-pressure rating or intermediate combinations thereof.

Integrated circuit with improved power supply distribution

Abstract: An integrated circuit with reduced size through improved power supply distribution. A bonding pad supplies V SS to an integrated circuit memory, which is distributed through a plurality of power supply lines in a first metal layer and a plurality of grid lines in a second metal layer intersecting at right angles. The plurality of grid lines are placed in unused spaced in the second metal layer and are coupled to the power supply lines in the first metal layer. Together the grid lines and the power supply lines provide an improved power supply by lowering the impedance from a point on the integrated circuit to V SS supplied on the bonding pad. While this technique is ideally suited to memory devices because of the repetitive nature of blocks of memory cells, other types of integrated circuits can also utilize such a power supply distribution technique.

A direct memory access controller using prioritized interrupts for varying bus mastership

Abstract: A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership The CPU only informs the DMAC of the highest priority cumulative interrupt priority With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC

Means and method for testing integrated circuits attached to a leadframe

Abstract: Apparatus and method of testing integrated circuits after the leads have been trimmed and partially formed, but before the package has been removed from the leadframe. One stage of a progressive trim and form process is adapted to test the integrated circuits by providing a membrane test head positioned underneath the IC package, wherein the membrane test head is coupled to an external tester. After the leads are electrically separated from each other end from the leadframe, the leads are aligned to the membrane test head and an inflatable bladder, which is positioned underneath the membrane test head, is inflated to couple the membrane test head to the leads. In this manner, one or more integrated circuits can be tested while still attached to the leadframe.

Method of fabricating a lateral semiconductor structure including field plates for self-alignment

Abstract: A method of fabricating a lateral semiconductor structure includes providing a semiconductor substrate and forming wells therein. Following formation of a dielectric layer on the substrate, field region openings are formed through which field regions are implanted into the substrate. The self-aligned formation of field oxidation regions to the field region openings then occurs and is followed by the formation of field plates on the field oxidation regions. A first active device region is then formed in said substrate, the formation of which is self-aligned to the field plates. This is followed by the formation of a second active device region in the first active device region which is also self-aligned to the field plates. The resulting structure allows for high speed devices that maintain consistently high current gain without sacrificing Early or breakdown voltages.

Operational amplifier having improved digitally adjusted null offset

Abstract: An operational amplifier is provided having a null offset that may be digitally adjusted quickly and accurately. The operational amplifier includes a cascode current mirror in an output stage wherein a small portion of current in the cascode current mirror is diverted away into a digitally controlled current divider. The more current that is diverted away, the larger the differential voltage that is created between the inverting and noninverting inputs of the operational amplifier. The current is increased until the output of the operational amplifier switches from the positive supply voltage to the ground supply voltage or vise versa. Additionally, a compensation capacitor at the output of the operational amplifier is switched out of the circuit during adjustment to speed up the null offset adjustment. Because the current being adjusted is not directly at the inputs of the operational amplifier the common mode input range is not deteriorated.

Frequency synthesizer with dynamically programmable frequency range of selected loop bandwith

Abstract: A frequency synthesizer which includes at least one phase lock loop operative in a selected loop bandwidth state includes a dynamically programmable control circuit for setting the frequency range of its selected loop bandwidth state. In another aspect, the frequency synthesizer may include a plurality of phase lock loop circuits; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to the plurality of phase lock loop circuits for setting a common frequency range for the loop bandwidth states of all of the phase lock loop circuits. In still another aspect, the frequency synthesizer includes a phase lock loop circuit; and a bias circuit programmably operative to generate at least one bias signal which is coupled to the phase lock loop circuit for setting a reference frequency range of the loop bandwidth states thereof, the phase lock loop circuit being dynamically programmable to vary the frequency range settings of the loop bandwidth states in relation to the reference frequency range set by the bias circuit.

Method of fabricating a high performance bipolar and MOS device

Abstract: An improved method of fabricating a high performance bipolar and MOS integrated circuit is provided. The method utilizes a single polysilicon layer, a self-aligned emitter-base structure, self-aligned silicide contacts, and silicon dioxide sidewall spacers to obtain reduced emitter and base resistance, reduced collector to base capacitance, greater switching speed, and a higher packing density. The method also has the advantage of being simple and compatible with a method of fabricating MOS devices which improves performance and yield.

Diagnostic mode for a frequency synthesizer

Abstract: A built in test circuit within a frequency synthesizer for use in selective call radio receivers provides a selectable one of a plurality of internal signals as a test signal for diagnosing the frequency synthesizer's output in real time.

Microprocessor which optimizes bus utilization based upon bus speed

Abstract: A data processing apparatus having a bus speed counter for determining the bus speed of a previous bus cycle. This previous bus speed information is then used to optimize bus utilization. This bus speed information is particularly useful for determining whether to run prefetch bus cycles during the execution of a conditional branch instruction. If previous bus cycles have been slow, prefetch procrastination can occurs until the branch condition resolves.

Low power peak detector/buffer with fast charge-up time

Abstract: A peak detector circuit that provides a signal at an output terminal which represents the most positive peak voltage level applied at an input terminal. Comparator circuit is coupled to the input terminal and to the output terminal to determine which voltage signal thereof is more positive to provide an output current whenever the supplied input voltage exceeds the voltage at the output terminal. The output current is then amplified for providing a current to a capacitor circuit for developing a voltage across the capacitor equal to the positive peak voltage level applied at the input terminal. A buffer circuit coupled to the capacitor circuit transforms the voltage across capacitor circuit to the output terminal and includes a clamping circuit for clamping coupled between the output terminal and the comparator circuit to prevent the comparator circuit output from saturating whenever the voltage applied at the input terminal is less than that appearing at the output terminal.