Showing papers by "Freescale Semiconductor published in 1991"

Low resistance probe for semiconductor

Abstract: A probe (10) that can be used for forming a low resistance electrical connection to a semiconductor die includes a contact (18) that is created on a compliant layer (12) which is supported by a substrate (11) Pressure applied to the contact (18) compresses the compliant layer (11) which causes a distal end of the contact (18) to move in a motion that is substantially equal to an arc As the contact (18) moves through the arc motion, it scrubs across a bonding pad of a semiconductor die and breaks through oxide that typically forms on the bonding pad thereby forming a low resistance electrical connection to the bonding pad

Method for fabricating a multichip semiconductor device having two interdigitated leadframes

Abstract: A packaged semiconductor device is disclosed having at least two electronic components encapsulated in a single body of standard size and pin-out configuration. In accordance with one embodiment of this invention, two leadframes, having electronic components electrically coupled thereto, are positioned such that the electronic components are in a stacked relationship and the outer portions of the two sets of leads within each leadframe are interdigitated. The configuration enables all components to be accessed independently and minimizes the footprint of the device while maintaining a standard package outline.

mic random access memory

Abstract: A DRAM is operated based upon an external clock input, a column enable, and a row enable The DRAM is accessed and row and column addresses are latched into buffers based upon the clock input

Method for forming pitch independent contacts and a semiconductor device having the same

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Shielded semiconductor device package

Abstract: A shielded semiconductor package and a method for manufacturing the package is provided. The shielded semiconductor package comprises a metal coating (19) applied over an encapsulated semiconductor device (16). The device may be transfer molded or encapsulated by glob top technology. The metal coating (19) serves as a barrier to the transmission of electromagnetic or radio frequency energy, thereby shielding the semiconductor device (16). The shielded semiconductor package is manufactured by providing a metallization pattern (12 and 14) on a substrate (10) and mechanically attaching and electrically interconnecting a semiconductor device (16) to the metallization pattern. A resin (18) is transfer molded about the semiconductor device, the electrical interconnections (17), and the metallization pattern so as to form an assembly, and a metal coating (19) is applied via vacuum deposition or plating to interconnect with a portion of the metallization pattern.

Multiple integrated circuit module which simplifies handling and testing

Abstract: A multi-chip module (26) used to interconnect and house a plurality of integrated circuits (10). The module (26) employs an intermediate structure referred to, herein, as a bridge chip (12). The bridge chip (12) connects the integrated circuit (10) to the module substrate (19). The integrated circuit (10) is attached to the bridge chip (12) and forms a composite structure (18) which can be burned-in and tested as an individual unit. The bridge chip (12) has interconnects to bring out the inputs and outputs of the integrated circuit (10). The composite structure (18) is mounted to the module substrate (19) such that, the integrated circuit (10) has a thermal pathway to the module substrate (19), and the bridge chip (12) connects to the module substrate (19). The module substrate (19) has interconnects to connect the plurality of composite structures (18).

Process for fabricating a silicon on insulator field effect transistor

Abstract: A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).

Method of making a transfer molded semiconductor device

Abstract: A method of making a pad array chip carrier package is disclosed. A semiconductor device (10) is bonded to a ceramic substrate (12). The semiconductor device may be attached to the substrate by wirebonding, tab bonding or flip chip bonding. The bonded assembly (16) is then attached to a flexible temporary support substrate (18) by means of an adhesive (19). The entire assembly is then placed into a mold cavity (20 and 22) and registered against the temporary support substrate (18). Plastic material (30) is molded about the semiconductor device and associated wirebonds in order to encapsulate the device. After removal from the mold, the encapsulated assembly is removed from the temporary support substrate (18) by peeling the temporary support substrate (18) from the circuit substrate.

Method for making a thermally enhanced semiconductor device by holding a leadframe against a heatsink through vacuum suction in a molding operation

Abstract: A method for making a semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounting surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads are encapsulated in a package body. Also incorporated into the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

Memory system having two-level security system for enhanced protection against unauthorized access

Abstract: A memory system, having security against unauthorized accessing of the contents of the memory system, comprises a first alterable memory (6), a second non-alterable memory (14, 16) and a data bus (5) for allowing external access to data stored in the memory system during a test mode of operation. The first alterable memory (6) comprises an options register (10) having a security bit (SEC) which, when programmed to an active state, prevents external access to the data stored in the first alterable memory during the test mode. The first alterable memory (6) further comprises a first data memory (8) having at least one security byte (VALSEC) which, when programmed to a predetermined state, prevents external access to the data stored in both the first alterable memory (6) and the second non-alterable memory (14, 16) during the test mode.

Method for forming a nested surface capacitor

Abstract: A nested surface capacitor and method of formation. The nested surface capacitor has a substrate (14) and an overlying dielectric layer (16). Conductive layer (18) overlies the dielectric layer (16). Three conductive cylindrical structures respectively referred to as an inner cylinder (30), a central cylinder (22') and an outer cylinder (32) overlie the conductive layer (18). The inner cylinder (30) lies within the central cylinder (22'). The central cylinder (22') lies within the outer cylinder (32). Together, the conductive layer (18) and the cylinders (30, 22', and 32) form a first electrode for the nested surface capacitor. A dielectric layer (38) overlying the cylinders (30, 22', and 32) and the conductive layer (18) acts as a capacitor dielectric. A conductive layer (40) overlying the dielectric layer (38) forms a second electrode of the capacitor.

Data processor with concurrent static and dynamic masking of operand information and method therefor

Abstract: A data processing system (10) implements a static and a dynamic masking operation of operand information concurrently. A static mask implements a conditional mask of a predetermined number of bits specified by the user and is determined prior to a comparison operation between the breakpoint address stored in a breakpoint register (24) and a logical address transferred via a logical address bus (11). A dynamic mask value implements a variable mask which allows the data processing system to mask the breakpoint address according to the size of a breakpoint address access. The static mask value and the dynamic mask value are concurrently implemented using a specialized bit cell (60) contained in both the breakpoint register (24) and the CAM array (26). The specialized bit cell (60) is comprised of two transistors (62 and 64) to concurrently mask a respective bit of operand information during a comparison operation.

Process for fabricating a semiconductor device using re-ionized rinse water

Abstract: A process for fabricating a semiconductor device uses re-ionized water, such as carbonated water, to rinse the device while preventing microcorrosion of metal layers. In one embodiment of the invention, a semiconductor wafer is provided having an overlying metal layer and a patterned layer overlying the overlying metal layer. Selected portions of the overlying metal layer are etched using the patterned layer as an etch mask. The patterned layer is removed by immersing the device in an organic solution without affecting the remaining metal layer. The device is then rinsed in a reservoir of re-ionized water to remove the organic solution from the device while preventing microcorrosion of the remaining metal layer.

Transistor having a lightly doped region and method of formation

Abstract: A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

Adaptive lock time controller for a frequency synthesizer and method therefor

Abstract: An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked. The control signal selector selects the first control signal during the predetermined time interval when the phase unlocked condition is detected, and the second control signal when the phase locked condition is detected.

Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing

Abstract: A method for semiconductor wafer scribing utilizing perforated metal areas in the scribe regions. In one form, a method for fabricating a semiconductor device includes forming a plurality of semiconductor die (12) on a semiconductor wafer (10) such that the die are separated from one another by scribe regions (13). A test structure (14) is formed within one of the scribe regions and includes a perforated probe pad (16). In one embodiment, the probe pad is perforated by a plurality of slots (18). The perforations in the probe pad aid in scribing the semiconductor wafer by preventing metal lift-off which often occurs when cutting metal areas.

Solder plate reflow method for forming a solder bump on a circuit trace intersection

Abstract: A method for forming a solder-bumped circuit trace on a planar dielectric substrate includes fabricating a trace having an intersection between linear section, depositing onto the trace a uniform thin plate of solder alloy and reflowing the solder alloy to form a bump at the intersection. More particularly, the trace comprises first and second linear sections that intersect at an angle between 45 degrees and 135 degrees and have widths preferably between 50 and 150 microns. The solder plate is deposited, preferably by electroplating, at a thickness between about 10 and 25 microns. Thereafter, when the trace is heated to melt the solder layer, the solder coalesces at the intersection to form the bump.

Dynamic random access memory with improved page-mode performance and method therefor having isolator between memory cells and sense amplifiers

Abstract: A dynamic random access memory includes memory cells located at intersections of word lines and differential bit line pairs. A row decoder activates a word line in response to a row address. A first sense amplifier coupled to each bit line pair then increases the small differential voltage of the bit line pair to positive and negative power supply voltages. The first sense amplifier is then isolated from the bit lines so that the bit lines may be equalized. The contents of memory cells along the activated word line are stored in corresponding first sense amplifiers, and the memory functions as a by-one static random access memory during successive page-mode cycles. At the end of the page-mode cycles, the first sense amplifiers are recoupled to the bit lines, and second sense amplifiers update modified data and refresh the charge stored in the memory cells. Performance is improved in at least three ways, including improved write speed, decreased SER by reducing subthreshold leakage, and reduced power consumption.

Semiconductor device having low source inductance

Abstract: A semiconductor device having a low source inductance are fabricated by having a maximum of two sources each in contact with a region which makes contact to a substrate or back side of the device. The back side source contact also allows the device to be mounted directly to a grounded heatsink.

Integrated circuit memory device and structural layout thereof

Abstract: A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

Vibration monolithic gyroscope

Abstract: A vibration gyroscope including a central mounting post and a planar mass symmetrically affixed thereto for vibrational movement. The post and mass are formed from a single layer of semiconductor material deposited on a substrate, such as silicon. Capacitive plates positioned below and above the mass, formed by depositing two additional layers of semiconductor material, are utilized for driving the mass and sensing vibration produced by the Coriolis effect.

Low-voltage precision current generator

Abstract: A low voltage precision current generator includes an amplifier, a first transistor, a current portion, and an output portion. The amplifier has first and second input terminals and changes an output voltage until voltages at the first and second input terminals are equal. An input voltage which may be a stable reference voltage or a variable voltage is received at the first input terminal. The second input terminal is connected to the current portion in order to provide a reference current proportional to a voltage difference between the voltage at the second input terminal and a power supply voltage. The amplifier controls the conductivity of the first transistor in order to regulate the voltage at its second input terminal. A precision current precision current proportional to the reference current is then provided.

DTMF detection having sample rate decimation and adaptive tone detection

Abstract: A method of dual-tone multifrequency (DTMF) detection which decimates and adaptively filters an input signal is provided to efficiently detect a presence of a DTMF signal. The input signal is provided to a half-band filter (14) to be decimated in frequency in accordance with Nyquist's theory. A decimated input signal is subsequently processed to form a low frequency component signal and a high frequency component signal. The low frequency component signal is again decimated by a decimator (24). The decimated low frequency component signal and the high frequency component signal are each filtered by an adaptive fir filter (22, 26) to provide a first and a second frequency parameter and a first and a second gain factor, respectively. The first and second frequency parameters and the first and second gain factors are then tested by a tone identifier (28) to determine if the input signal includes a valid DTMF signal.

Bandgap voltage reference circuit

Abstract: A bandgap voltage reference circuit (50, 100) which operates at low power supply voltages provides a reference current as either a one- or a two-ΔVBE voltage across a first resistor (82, 133). A current proportional to the reference current is mirrored into one terminal of a second resistor (94, 133) to provide the bandgap voltage. Compensation for base currents injected into the circuit (50, 100) by two transistors forming the ΔVBE reference is provided. In one embodiment (50), base currents of first (66) and second (87) transistors which have equal emitter areas and collector current density as the two transistors (68, 85) forming the ΔVBE reference compensate for the injected base currents. In another embodiment (100), a single transistor (127) injects current substantially equal to the sum of the base currents of the two transistors (116, 121) forming the ΔVBE reference. The single transistor (127) has twice the emitter area of one of the transistors (116) forming the ΔVBE reference.

Static RAM with test features

Abstract: A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.

Pipelined data processor which conditionally executes a predetermined looping instruction in hardware

Abstract: A data processor (10) having an instruction fetch unit (12), a decode and control unit (14), and an execution unit 16 performs conditionally executed instructions in hardware. A conditional break instruction, BRKcc, is inserted within a looping instruction to conditionally terminate the looping instruction with a minimum number of instruction cycles. A conditional do-loop instruction, DO#0, prevents the data processor (10) from executing a do-loop with a loop count within a loop counter (24) of zero upon entry. A conditional repeat instruction, REP#0, prevents a repeat instruction from being executed if a loop count is zero upon entry. A conditional repeat instruction, REPcc, allows a subsequent instruction to be conditionally terminated during execution.

High frequency linear amplifier assembly

Abstract: A wide bandwidth linear amplifier (10) that has an operating band in excess of 1 GHz mounts the high power dissipating components (11) of the amplifier (10), and the components 917, 18) that control the high frequency gain and stability of the amplifier (10) onto a daughter board (32) that has a high thermal conductivity The daughter board (32) and the remaining circuit components (21, 22, 23, 24, 26a, 26b) are then mounted on a mother board (31) that has a lower thermal conductivity The assembly (30) reduces the circuit's parasitic inductance (46, 47, 48, 49) and parasitic capacitance (51, 52), and provides unconditional stability at high frequencies

RF amplifier assembly

Abstract: A series resonant circuit (17, 16, 22, 21, 19) is employed to minimize the area utilized to form an RF amplifier (10). The series resonant circuit (17, 16, 22, 21, 19) utilizes a capacitor (21) along with inductors (17, 19, 22) that are formed by bonding wires (17, 19, 22) which interconnect the components of the amplifier (10). The series resonant circuit is tuned to the second harmonic of the fundamental frequency applied to the RF amplifier (10). The area consumed by the series resonant circuit (17, 16, 22, 21, 19) is small thereby minimizing the amplifier's size.

Semiconductor device having a particular lid means and encapsulant to reduce die stress

Abstract: A semiconductor device (20) has reduced die stress by incorporating a lid (30) which constrains the expansion and contraction of an encapsulant. In one embodiment, a semiconductor die (22) having an active surface (23) is coupled to a plurality of leads (24). An encapsulant (28) is disposed on the active surface. The lid (30) overlies the active surface (23) and is adhesively coupled to the semiconductor die (22) by the encapsulant (28). The lid is of a material which has a coefficient of thermal expansion which closely approximates that of the semiconductor die in order to prevent stress build-up in the die which is normally caused by higher rates of expansion and contraction of the encapsulant in comparison to the those of the semiconductor die.

Semiconductor device having a multilayer leadframe with full power and ground planes

Abstract: A semiconductor device (10) has a multilayer leadframe (14) with two full voltage planes, specifically an upper voltage plane (16) and a lower voltage plane (18). A semiconductor die (12) is mounted to the upper voltage plane. Bond pads (13) of the die are electrically coupled to appropriate leads (20a, 20b, and 20c) using conductive wires (22). Upper voltage plane (16) is provided with at least one opening (28) to allow passage of a conductive wire through the opening in order to electrically couple a bond pad or a lead to lower voltage plane (18). The voltage planes are attached to the leadframe using welded conductive tabs (24), an electrically insulating adhesive layer (26), or both.