Showing papers by "Freescale Semiconductor published in 1992"

Overmolded semiconductor device having solder ball and edge lead connective structure

Abstract: A low cost manufacturing method is used to fabricate a small multiple chip semiconductor device (10). In one embodiment, a first pattern of conductive traces (14) is formed on one surface of a substrate (12), and a second pattern of traces (16) is formed on a second surface of the substrate (12). A first semiconductor die (20) is interconnected to the first traces (14), and a package body (24) is formed around the first die and a portion of the traces. A second semiconductor die (26) is interconnected to the second traces (16) on the second surface. A second package body (28) is formed around the second die and a portion of the traces (16). Solder balls (32) are coupled to exposed portions of the second traces (16) around the perimeter of the package body (28) to establish external power and ground connections to each die. Edge leads (36) are externally soldered to the traces (14 & 16) around the periphery of the substrate (12) to establish remaining electrical connections.

Stacking three dimensional leadless multi-chip module and method for making the same

Abstract: A stackable three dimensional leadless multi-chip module (10) is provided whereby each level of semiconductor device (11) is interconnected to another level through reflowing of solder plated wires (22). Each semiconductor device (11) contains a semiconductor die (24) overmolded by a package body (12) on a PCB substrate (14) having a plurality of edge metal conductors (16) that form half-vias (18). The half-vias (18) at the edges of substrate (14) give the substrate a castellated appearance, where the castellations serve as the self-aligning feature during the stacking of the devices (11). Each device (11) is simply stacked on top of each other without any additional layers to give the semiconductor module (10) a lowest possible profile. A plurality of solder plated wires (22) fits into the half-vias (18) and is solder reflowed to the metal conductors (16) to interconnect the semiconductor devices (11). The wires (22) are bent to enable the module (10) to be surface mounted to a PC board.

Semiconductor memory device and method of formation

Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.

Method for forming a transistor having silicided regions

Abstract: A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

Apparatus and method for optimizing performance of a cache memory in a data processing system

Abstract: A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both instruction cache unit (26) and sequencer (34) to provide necessary control and address information to load/store unit (28). Load/store unit (28) sequences execution of each of the instructions, and provides necessary control and address information to data cache unit (24) at an appropriate point in time. Cache control logic (60) subsequently processes both the address and control information to provide external signals which are necessary to execute each of the cache control instructions. Additionally, cache control logic (60) provides an external transfer code signal which allows a user to know when a cache transaction is performed.

Method for solder application and reflow

Abstract: A method for applying solder on a substrate (12) comprises the steps of providing a substrate (12) having predefined solder pads (15) and then providing solder spheres (16) for suitable placement on the solder pads. Then applying flux (14) and tacking media (18) between the solder pads (15) and the solder spheres (16) and then placing the solder spheres on the solder pads. Subsequently the solder spheres are heated onto the solder pads of the substrate providing reflowed solder (26) on the solder pads. Then a layer of flux tacking media (28) is applied on the reflowed solder. Next, a component (30 or 40) is placed on the reflowed solder and flux tacking media providing a substrate assembly (10). Finally, the circuit assembly is heated allowing the component to be soldered to the solder pad.

Method for making a self-aligned vertical thin-film transistor in a semiconductor device

Abstract: A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current electrode (26) is formed on a bottom surface of the trench while a second current electrode (28) overlies the first dielectric material, each current electrode preferably being formed of polysilicon. A channel region (30) connecting the first and second current electrodes lies along the vertical wall of the trench and has a length substantially equal to the predetermined depth. A control electrode (36) is located within the trench and is also preferably formed of polysilicon. The control electrode is electrically isolated from the first current electrode and the channel region by a second dielectric layer (32).

Microprocessor having environmental sensing capability

Abstract: A microprocessor having a monolithically integrated environmental sensor is provided. The microprocessor is shielded from an environmental signal by isolation which is specific to the type of sensor used, thereby allowing the sensor to be exposed to the environmental signal. Optionally, high current drive circuitry is integrated with the microprocessor-sensor circuit to provide a monolithic device which allows control of power loads based in part on output from an environmental sensing device.

Method and apparatus for asynchronous timing recovery using interpolation filter

Abstract: In an asynchronous communication system such as a V.32 modern (80), an input signal is sampled at a near-end clock rate. Each sample is then interpolated in an interpolation filter (92) to provide corresponding interpolated values. The interpolation filter (92) uses a selected one of a predetermined number of sets of windowed sinc function coefficients, each set having a successively greater phase offset. A time drift between near-end and far-end clocks is measured by tracking the coefficient shift in a passband phase-splitting, fractionally-spaced equalizer (95). When the time drift exceeds a threshold, a subsequent set of windowed sinc function coefficients is selected. When the time drift exceeds the threshold after the last set of coefficients is used, the first set is again selected and an interpolated value is either dropped or repeated in forming the far-end data samples.

Apparatus and method for handling fragile semiconductor wafers

Abstract: An apparatus (60) which handles fragile semiconductor wafers (21) adhesively mounted to a submount (22) using a high temperature wax is provided The apparatus (60) includes a vacuum chuck (24) for holding a first surface of the wafer (21) and a solvent chamber (11, 11') for applying solvent to the back surface of the submount (22) The apparatus (60) includes an enclosure (29) for providing an inert gas environment around the solvent chamber (11, 11'), the wafer (21), and the vacuum chuck (24) The apparatus (60) further includes a means for remounting (30) the wafer (21) to a submount (22) using a low temperature wax after the high temperature wax is dissolved The wafer (21) is then released from the vacuum chuck (24) and the first surface of the wafer (21) is mounted to an adhesive tape (34) Following the mounting, the low temperature wax is dissolved or melted to demount the wafer (21 ) from the submount (22), leaving the wafer (21) securely mounted on the adhesive tape (34) for sawing

Rule based floorplanner

Abstract: A rule based floorplanner for a macrocell array having a plurality of predetermined macrocells. The floorplanner uses a net list (23), a macrocell list (26), and a list of design constraints (31) and characteristics of the base array itself to derive an initial Burain score. A trial floorplan is attempted (33) and checked against a list of theoretical rules (39) and a list of empirical rules (38) to determine a measured Burain score (36) which accurately indicates the difficulty which can be expected when completing the design.

Automatic A/D converter operation using a programmable control table

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Method for forming a via structure and semiconductor device having the same

Abstract: A semiconductor device (20) makes contact between a first metal line (22) and an overlying second metal line (24) without the need for a conductive landing pad. Sidewall spacers (30) are formed adjacent sides of metal lines (22) such that during formation of a via (34) in an overlying dielectric layer (32), the sidewall spacer prevent trenching of underlying dielectric layer (28) if the via is misaligned. The sidewall spacers are formed of a dielectric material which has an etch rate which is significantly slower than the etch rate of dielectric layer (32). In another embodiment, portions of the sidewall spacers are selectively removed prior to depositing a second metal layer (42). Upon depositing the second metal layer, the side of metal line (22) is locally clad with the second metal to increase contact area and lowering contact resistance.

Method and apparatus for performing power on reset initialization in a data processing system

Abstract: A method and apparatus for performing power on reset initialization in a data processing system (40). In one form, the present invention uses a circuit (71) to ensure that a node (65) always power up to the correct logic level. This node (65) can then be used to initialize a latch (83) so that the latch (83) always drives a predetermined logic level at its data output when the latch (83) powers up. The data output of latch (83) is a Power On Reset signal which is asserted during power on reset initialization and which is negated when power on reset initialization is completed.

Method and apparatus for switching between gain curves of a voltage controlled oscillator

Abstract: A method and apparatus for switching between gain curves of a switched gain voltage controlled oscillator (VCO) 52, 52' or 52" In one form, the present invention uses a switched gain voltage controlled oscillator (VCO) 52, 52' or 52" which utilizes a ring oscillator A Gain Control signal is used to select between using a high gain curve and using a low gain curve The low gain curve is produced by selecting a high resistance path to either power or ground The high gain curve is produced by selecting a low resistance path to either power or ground

Method of formation of vertical transistor

Abstract: A method for forming a vertical transistor (10) begins by providing a substrate (12). A conductive layer (16) is formed overlying the substrate (12). A first current electrode (26), a second current electrode (30), and a channel region (28) are each formed via one of either selective growth, epitaxial growth, in-situ doping, and/or ion implantation. A gate electrode or control electrode (34) is formed laterally adjacent the channel region (28). A selective/epitaxial growth step is used to connect the conductive layer (16) to the control electrode (34) and forms a control electrode interconnect which is reliable and free from electrical short circuits to the current electrodes (26 and 30). The transistor (10) may be vertically stacked to form compact inverter circuits.

Method for forming a transistor having a dynamic connection between a substrate and a channel region

Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Semiconductor memory cell having a trench structure

Abstract: In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).

Semiconductor device having window-frame flag with tapered edge in opening

Abstract: A semiconductor device (30) utilizes a lead frame (32) having a window-frame flag (36). An opening (44) within the flag creates an interior edge (46) which is tapered, preferably to an angle φ that is between 55° and 65°. The tapered interior edge reduces boundary-layer separation of a resin molding compound during formation of a resin package body (42). Thus, voids in the resin packaging material near the interior edge of the flag are less likely to be formed.

Repairable semiconductor multi-package module having individualized package bodies on a PC board substrate

Abstract: A semiconductor multiple package module (10) on a PCB material substrate (18) is provided, wherein semiconductor dice are directly mounted onto the PCB material substrate (18) thereby eliminating a subsequent board mounting at the customer level. A plurality of semiconductor dice are mounted and electrically connected to a plurality of circuit traces (22) on the PCB material substrate (18) having a plurality of edge connectors (20). The plurality of circuit traces (22) has conductive paths to electrically interconnect the semiconductor dice to the edge connectors (20) and to each other. The semiconductor dice are directly overmolded on the PCB material substrate (18) with a molding compound to form individual semiconductor devices (12, 14, and 16) having separate package bodies. The individualized package bodies enable repair to the module by making removal of only nonfunctional semiconductor devices from the PCB material substrate (18) possible.

Monotonic current/resistor digital-to-analog converter and method of operation

Abstract: A digital-to-analog converter (10) performs two distinct conversions (12,59) of most significant bits (MSBs) and least significant bits (LSBs), respectively, of a digital input signal and uses the conversion results to provide an equivalent analog output. A plurality of current sources (34-36) is controlled by a thermometer code equivalent value of the most significant bits to provide a first input current to an output stage (22). A plurality of resistors (60-63) is controlled by a binary to `one of` equivalent of the least significant bits to provide a second input current to the output stage. The output stage (22) converts a combination of the first and second input currents to the analog output.

Method for forming a raised vertical transistor

Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).

CMOS device and process

Abstract: A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.

Method and apparatus for testing an analog to digital converter

Abstract: A method and apparatus for testing an analog to digital converter (14) having a capacitor digital to analog converter (30). In one form, the analog to digital converter uses a small amount of capacitor test logic (44) to test for opens and shorts in the capacitor array (42), the switch logic (38), and the decode logic (36). Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by using AND and OR logical functions. As a result of using capacitor test logic (44), a very quick pass/fail functional test can be performed on the analog to digital converter (14) without requiring the analog to digital converter (14) to perform time-consuming analog to digital conversions.

Tuning circuit for use with an integrated continuous time analog filter

Abstract: A tuning circuit (10) and method of operation for tuning an analog filter (40). The tuning circuit (10) has an integrator with an input portion (12) and a comparator portion (14), a counter (32), and a decoder (34). The integrator is implemented with an RC time constant which is proportional to an RC time constant of the analog filter (40). The comparator portion (14) provides an enable signal during the RC time constant of the integrator to the counter (16) which quantizes the RC time constant relative to a clock period of the counter (16). A predetermined decoding is performed to provide an output control signal to control adjustment of the RC time constant of the analog filter (40).

In a data processor a method and apparatus for performing a floating-point comparison operation

Abstract: A data processor (10) has a floating-point execution unit (32) for executing a floating-point compare operation using two data operands. The execution unit (32) uses mantissa comparator logic (107) to perform a bit-wise comparison of a mantissa portion of a first operand with the mantissa portion of a second operand, and to provide a mantissa comparison result. Similarly, exponent comparator logic (122) performs a bit-wise comparison of an exponent portion of the first operand with the exponent portion of the second, and provides an exponent comparison result. Comparator logic (114) in the execution unit receives the mantissa comparison result and the exponent comparison result. If the exponent portions of the two operands are not equal, the comparator logic (114) uses an operand sign bit of each operand and the exponent comparison result to order the two operands. If the exponent portions of the two operands are equal, the comparator logic uses the operand sign bit of each operand and the mantissa comparison result to order the two operands.

Decoder/comparator and method of operation

Abstract: A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A1, A2, A3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.

High-permittivity dielectric capacitor for use in a semiconductor device and process for making the same

Abstract: A high-permittivity dielectric capacitor (28) having a refractory-metal oxide layer (16) framing the first electrode (14) of the capacitor (28) and separating a high-permittivity dielectric layer (24) from an insulating layer (12) underlying the capacitor (28). The high-permittivity dielectric layer (16) makes contact with the first electrode (14) through an opening (18) in the refractory-metal oxide layer (16). The refractory-metal oxide layer (16) separates the high-permittivity dielectric layer (24) from the insulating layer (12) in all regions away from the opening (18) in the refractory-metal oxide layer (16). During fabrication of the capacitor (28), when the high-permittivity dielectric layer (24) is patterned, the refractory-metal oxide layer (16) provides an etch-stop.

Leadframe strip for semiconductor packages and method

Abstract: A substantially planar insulating sheet of high temperature printed circuit board material (11) is used to form a leadframe strip (18, 19, 21) for a semiconductor package (20) The leadframe strip (18, 19, 21) includes a die attach opening (12) through the insulating sheet (11) A plurality of metallized areas (13, 22, 23) on the insulating sheet (11) form bonding pads (13) and package leads (22) Conductive holes (14) electrically connect the bonding pads (13) and the package leads (22)

Bond inspection technique for a semiconductor chip

Abstract: A bond inspection technique which determines the integrity of a plurality of package leads (13) bonded to a plurality of contact areas (12) on a semiconductor chip (11). A bonding process heats each package lead (13) bonded to each contact area (12). A camera (16) forms an infra-red intensity image at a predetermined time of the semiconductor chip (11) and ports image data to a computer (18). Infra-red intensity radiated from each bond on the semiconductor chip (11) is compared by the computer (18) with infra-red intensity data of known good and bad bonds. The comparison of each bond determines bond integrity of the semiconductor chip (11).