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Showing papers by "Freescale Semiconductor published in 1995"


Patent•
10 Jul 1995
TL;DR: In this paper, a data processor (10) has a single test controller (11), the test controller has a test pattern generator portion (26) and a memory verification element (27).
Abstract: A data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.

155 citations


Patent•
03 Jan 1995
TL;DR: In this paper, a passive element (10) has an insulating layer (12) overlying a silicon substrate (14), and a metal layer (16) comprising a signal line (18) and a groundplane (20) is disposed overlying the groundplane.
Abstract: A passive element structure and method for a microwave integrated circuit reduces signal propagation losses. In one approach, a passive element (10) has an insulating layer (12) overlying a silicon substrate (14). A metal layer (16) comprising a signal line (18) and a groundplane (20) is disposed overlying the insulating layer (12), and at least a portion of the metal layer (16) contacts the substrate (14) through at least one opening (22, 24) in the insulating layer (12). The silicon substrate (14) has a resistivity greater than 2,000 ohm-cm, and the passive element (10) preferably carries signals having frequencies greater than 500 MHz. Signal losses in the passive element (10) are minimized because the charge density at the surface (15) of the substrate (14) underlying the metal layer (16) is significantly reduced. In one example, the passive element (10) is a coplanar waveguide transmission line.

155 citations


Patent•
13 Nov 1995
TL;DR: In this paper, a cache line is merged with the cache line prior to storage in the cache and other matching entries become active and are allowed to reaccess the cache (71).
Abstract: A data processor (40) keeps track of misses to a cache (71) so that multiple misses within the same cache line can be merged or folded at reload time. A load/store unit (60) includes a completed store queue (61) for presenting store requests to the cache (71) in order. If a store request misses in the cache (71), the completed store queue (61) requests the cache line from a lower-level memory system (90) and thereafter inactivates the store request. When a reload cache line is received, the completed store queue (61) compares the reload address to all entries. If at least one address matches the reload address, one entry's data is merged with the cache line prior to storage in the cache (71). Other matching entries become active and are allowed to reaccess the cache (71). A miss queue (80) coupled between the load/store unit (60) and the lower-level memory system (90) implements reload folding to improve efficiency.

111 citations


Patent•
02 Jun 1995
TL;DR: In this article, a high frequency bypass capacitor (36, 36') is built into a thin-film portion (16, 16') of a polymer carrier substrate (15) of a PBGA.
Abstract: A high frequency bypass capacitor (36, 36') is built into a thin-film portion (16, 16') of a polymer carrier substrate (15) of a PBGA (10). The carrier substrate (15) has both a stiffener (18) and a thin-film portion (16, 16') which has multiple metal layers (24, 28, 30, 32). The power supply planes (28, 30) of these metal layers are used to form built-in bypass capacitors (36, 36'), wherein the power supply planes are specifically designed to be adjacent and parallel layers. An ultra thin film laminate construction provides thin dielectric films (26) between the metal layers to allow the bypass capacitor to be placed very dose to the attached semiconductor die (12) to further reduce parasitic inductance and resistance between die connections (14) and the bypass capacitor. The built-in feature minimizes inherent parasitic series inductance and resistance, thus enabling the filtering of unwanted low pulse width glitches on a power plane connected to VLSI devices at operating frequencies at or above 100 MHz.

101 citations


Patent•
10 Oct 1995
TL;DR: In this paper, a graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12), a source region (13) and a drain region (14) are formed in the substrate region and are spaced apart to form a channel region (16).
Abstract: A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.

87 citations


Patent•
21 Aug 1995
TL;DR: In this article, a computer network comprising a trusted computer network and an untrusted computer network is described, and a plurality of firewall systems are used to provide controlled access between the trusted computer networks and the first untwusted computer networks.
Abstract: A computer network comprising a trusted computer network (16), and an untrusted computer network (17) A plurality of firewall systems (21) provide controlled access between the trusted computer network and the first untrusted computer network An Application layer bridge (22) establishes a transparent virtual circuit across the plurality of firewalls (21)

86 citations


Patent•
26 May 1995
TL;DR: In this article, the preferred integrated inductor (11) provides significant advantage over external inductors of the past with respect to simplicity of manufacture as well as system size and cost.
Abstract: An electronic device (10) comprises a copper integrated inductor (11) overlying other solid state components (31) of the device (10). Preferably, the copper inductor (11) is formed of plated copper to a thickness of several microns. The preferred integrated inductor (11) provides significant advantage over external inductors of the past with respect to simplicity of manufacture as well as system size and cost. Additionally, the preferred inductor (11) provides improved inductance per area, lower series resistance and higher Q values, relative to inductors of the past.

79 citations


Patent•
07 Aug 1995
TL;DR: In this article, a method and structure for reducing capacitance between interconnect lines (11, 24, 26) utilizes air gaps (17, 47, 47) between the interconnect line and a silane oxide layer (14) forms a "breadloaf" shape which can be sputter etched to seal the air gaps.
Abstract: A method and structure for reducing capacitance between interconnect lines (11, 24, 26) utilizes air gaps (17, 47) between the interconnect lines (11, 24, 26). Deposited over the interconnect lines (11, 24, 26), a silane oxide layer (14) forms a "breadloaf" shape which can be sputter etched to seal the air gaps (17, 47). Prior to the deposition of the sputter etched silane oxide layer (14), spacers (13, 42, 43) can be formed around the interconnect lines (11, 24, 26) to increase the aspect ratio of gaps (23, 31) between the interconnect lines (11, 24, 26) which facilitates the formation of the "breadloaf" shape of the silane oxide layer (14).

77 citations


Patent•
26 Jan 1995
TL;DR: In this article, a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), carrier channel allocations may be updated as follows.
Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), carrier channel allocations may be updated as follows. At periodic intervals, the primary site requests updating bit loading information from the secondary sites. Upon receiving the updated bit loading information, the primary site (102) determines an updated call bit loading table for each active call. From this, the primary site (102) determines whether current carrier channel allocation provides sufficient bandwidth. When the current carrier channel allocation does not provide the sufficient bandwidth, the primary site modifies the current carrier channel allocation to meet the bandwidth requirements.

73 citations


Patent•
20 Nov 1995
TL;DR: In this article, an apparatus and a method of dynamically mixing a slurry for a chemical mechanical polish includes pumping an abrasive (33) and an oxidizer (37) into a first portion (19) of the slurry mixer (11), using a magnetically coupled stirrer (17) to blend the abrasive and the oxidizer, and then transporting the slurghurry (41) through a diffuser (21) and into a second portion (22), keeping the slury (41), for a residence time, and, subsequently, using the sl
Abstract: An apparatus and a method of dynamically mixing a slurry for a chemical mechanical polish includes pumping an abrasive (33) and an oxidizer (37) into a first portion (19) of a slurry mixer (11), using a magnetically coupled stirrer (17) to blend the abrasive (33) and the oxidizer (37) into a slurry (41) in the first portion (19) of the slurry mixer (11), transporting the slurry (41) through a diffuser (21) and into a second portion (22) of the slurry mixer (11), keeping the slurry (41) in the second portion (22) of the slurry mixer (11) for a residence time, and, subsequently, using the slurry (41) to chemical mechanical polish a semiconductor substrate (43). The diffuser (21) reduces air entrainment of the slurry (41), and the residence time enables the slurry (41) to be used when it has a maximum polishing rate.

73 citations


Patent•
02 Nov 1995
TL;DR: In this article, a vertically raised transistor (10) is formed having a substrate (12), a conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor, and a first doped region (16a and 16b) and a second doped regions (16b) are each electrically coupled to the conductively plug region via sidewall contacts.
Abstract: A vertically raised transistor (10) is formed having a substrate (12). A conductive plug region (22) is selectively or epitaxially formed to vertically elevate the transistor (10). A first doped region (16a) and a second doped region (16b) are each electrically coupled to the conductive plug region (22) via sidewall contacts. The doped regions (16a and 16b) are used to form current electrode regions (26) within the conductive plug region (22). A channel region separates the current electrodes (26). A gate dielectric layer (28) is formed to overlie the channel region. A conductive layer (30) is formed to overlie the gate dielectric layer (28). Conductive layer (30) forms a gate electrode for the transistor (10). The vertical raised transistor (10) and conductive plug region (22) provide improved device isolation and improved device operation.

Patent•
25 May 1995
TL;DR: In this article, a semiconductor dielectric is formed by providing a base layer (12) having a surface, and a thin interface layer (13) is formed at the surface of the base layer, which has a substantial concentration of both nitrogen and fluorine.
Abstract: A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features which the nitrogen/fluorine interface further improves the dielectric's features.

Patent•
03 Jan 1995
TL;DR: In this paper, a sensor for detecting chemicals and changes in the surrounding environment utilizes a sol-gel sensor element (14,16,17,54,56,57) containing a chemical indicator.
Abstract: A sensor (10,30,40,50,70) for detecting chemicals and changes in the surrounding environment utilizes a sol-gel sensor element (14,16,17,54,56,57) containing a chemical indicator. Grooves (12,13,24,52,53) are formed in a substrate (11,51). The grooves are filled with a sol-gel material having a chemical indicator, and the sol-gel is cured to adhere to the substrate (11,51). The grooves (12,13,24,52,53) are formed to facilitate optically coupling a fiber optic cable (46) to the sol-gel sensor element. Light is coupled from the fiber optic cable (46) to the sol-gel sensor element (14,16,17,54,56,57).

Patent•
27 Mar 1995
TL;DR: A flip-chip structure and method connecting a semiconductor chip (11) having conductive bumps (16) to a substrate (12) having vias (19) extending from a first side to a second side (18) of the substrate as discussed by the authors.
Abstract: A flip-chip structure and method connects a semiconductor chip (11) having conductive bumps (16) to a substrate (12) having vias (19) extending from a first side (21) to a second side (18) of the substrate (12). A filler material (22) is deposited into the vias (19), and the conductive bumps (16) are inserted into the vias (19) for connecting the semiconductor chip (11) to a conductive element (17) covering the vias (19) on the second side (18) of the substrate (12).

Patent•
Mavin C. Swapp1•
02 Nov 1995
TL;DR: An integrated device test system (10, 40) having AC and DC measurement modes of operation comprises a drive circuit (11, 41), a programmable measurement unit (12), and a switch (18) as discussed by the authors.
Abstract: An integrated device test system (10, 40) having AC and DC measurement modes of operation comprises a drive circuit (11, 41), a programmable measurement unit (12) and a switch (18). The drive circuit (11, 41) may be a current mode drive circuit (11) or a voltage mode drive circuit (41). The drive circuit (11, 41) is coupled to the programmable measurement unit (12) and a device under test (64). In a DC mode of operation, the switch (18) is configured to couple a sense terminal (39) with one end of an isolation resistor (66). A second end of the isolation resistor (66) is connected to a pin (63) of the device under test (64). In an AC mode of operation, the switch (18) is configured to couple the sense terminal (39) with the drive circuit (11, 41) and the force terminal (35) of the programmable measurement unit (12).

Patent•
29 Sep 1995
TL;DR: In this article, the etch stop layer is used to expose the top of conductive interconnect, while maintaining a portion of the layer along a sidewall of the interconnect and particularly along those sidewall portions which contain aluminum.
Abstract: A method for forming vias in a semiconductor device improves the resistance and reliability of contacts formed by use of an etch stop layer during the via formation process. An etch stop layer (40), preferably a silicon nitride or aluminum nitride layer, is deposited over conductive interconnect (34). A via (44) is etched in interlayer dielectric (42), stopping on etch stop layer (40). Etch stop layer (40) is then anisotropicly etched to expose the top of conductive interconnect (34), while maintaining a portion of the etch stop layer along a sidewall of the interconnect, and particularly along those sidewall portions which contain aluminum. A conductive plug (54) is then formed in the via, preferably using one or more barrier or glue layers (50). Formation of a tungsten plug using tungsten hexafluoride can then be performed without unwanted reactions between the tungsten source gas and the aluminum interconnect.

Patent•
01 May 1995
TL;DR: In this article, a high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electrostatic discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body to form a monolithic high frequency integrated circuit structure.
Abstract: A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10) The high frequency power FET device (22) includes a grounded source configuration The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation

Patent•
01 Jun 1995
TL;DR: In this paper, a static random access memory cell with floating node capacitors is described, where the storage nodes act as the first plates for the floating nodes, and a conductive member acts as the second plates for floating nodes.
Abstract: A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

Patent•
30 May 1995
TL;DR: In this paper, the flip chip bumps (24, 26, and 27) and an inductor (17) are simultaneously fabricated on a semiconductor substrate and the fabrication process includes two electroplating steps.
Abstract: Flip chip bumps (24, 26, and 27) and an inductor (17) are simultaneously fabricated on a semiconductor substrate (10). The fabrication process includes two electroplating steps. The first step electroplates copper (18) onto a seed layer (13) to form the inductor (17) and a first portion (16) of the flip chip bumps (24, 26, and 27). The second step electroplates copper (21) onto the previously electroplated copper (18) to form a second portion (21) of the flip chip bumps (24, 26, and 27).

Patent•
10 Aug 1995
TL;DR: In this paper, an electro-optic integrated circuit including an addressable array of light emitting devices, a column decoder and a plurality of address lines formed on the substrate is presented.
Abstract: An electro-optic integrated circuit including an addressable array of light emitting devices, a column decoder and a plurality of address lines formed on the substrate. There are n=2{integer[log(m)/log(2)]+1}, where m equals the number of columns, address lines each including an external connection pad. The decoder includes a switching circuit connected to each column for activating the column and a plurality of sets of diodes connected to the address lines and the switching circuits so that each set of diodes has a unique code produced by a combination of diodes in that set and the address lines to which the diodes in that set are connected.

Patent•
29 Mar 1995
TL;DR: In this paper, the antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092).
Abstract: Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.

Patent•
03 Apr 1995
TL;DR: In this article, a conductive paste is disposed in openings of a wet photoresist layer before removing it, if the polyimide is photo-imagable or photo-realizable.
Abstract: Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.

Patent•
12 Jun 1995
TL;DR: In this article, a loop processor identifies all loop type instructions which are supplied by the instruction source, copies those instructions into a loop memory, and supplies those loop instructions to the single instruction multiple data array processor in the order received.
Abstract: An instruction accelerator which includes an instruction source, and a single instruction multiple data array processor which executes the instructions supplied by the instruction source. A loop processor identifies all loop type instructions which are supplied by the instruction source, copies those instructions supplied by the instruction source into a loop memory, and supplies those loop instructions to the single instruction multiple data array processor in the order received, at the rate required by the single instruction multiple data array processor, and as many times as required by the loop count field.

Patent•
24 Feb 1995
TL;DR: An anti-reflective coating (ARC) is formed over a reflective, conductive layer (18) such as polysilicon or aluminum, in a semiconductor device as discussed by the authors.
Abstract: An anti-reflective coating (ARC) (20) is formed over a reflective, conductive layer (18), such as polysilicon or aluminum, in a semiconductor device (10). The ARC is an aluminum nitride layer. During photolithography, the ARC absorbs radiation waves (30), particularly absorbing wavelengths under 300 nanometers, such as deep ultraviolet (DUV) radiation at 248 nanometers. Being absorbed by the ARC, the radiation waves are prevented from reflecting off the underlying conductive layer. Thus, resist mask (34) is patterned and developed true to the pattern on lithography mask (24), resulting in accurate replication into appropriate layers of the device.

Patent•
05 Dec 1995
TL;DR: In this article, a branch prediction mechanism for speculatively placing branch target instructions into the fetch, decode, dispatch, and execute pipeline when a branch is predicted to be taken is presented.
Abstract: A low-power pipelined data processor (20) includes a branch prediction mechanism for speculatively placing branch target instructions into the fetch, decode, dispatch, and execute pipeline when a branch is predicted to be taken. To save power the data processor (20) selectively disables one or more pipeline resources (24) associated with placing the branch target instructions into the pipeline according to the strength of the prediction. If the prediction is weakly not taken, the data processor (20) enables the pipeline resource (24) to prevent disruptions to the pipeline if the branch resolves as taken during the cycle. However if the prediction is strongly not taken, the pipeline resource (24) is disabled to save power, which outweighs the infrequent resolution to taken. In one embodiment, the data processor (20) disables a branch target instruction cache (24) if history bits corresponding to the branch instruction stored in a branch history table (26) indicate strongly that the branch will not be taken.

Patent•
05 Sep 1995
TL;DR: In this article, a switchable current source (41) is one of many required by a DAC to convert a digital signal to an analog signal, which enables or disables the current source from providing or not providing a current.
Abstract: A switchable current source (41) for a Digital to Analog Converter (DAC) to reduce noise glitches when a change in total current provided by the DAC occurs The switchable current source (41) is one of many required by a DAC to convert a digital signal to an analog signal Each current source of the DAC receives an input voltage that enables or disables the current source from providing or not providing a current A sampled input voltage is alternately provided to the switchable current source (41) by a first flip flop (42) or a second flip flop (43) One flip flop samples the input voltage while the other provides a previous sampled input voltage for enabling and disabling the switchable current source (41) Switches (46,47) couple an output voltage of the first or second flip flops (42,43) a predetermined time after the output voltage changes to a transistor (51) coupled to a current source (53)

Patent•
17 May 1995
TL;DR: A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36), which generates a first and a second result from supplied operands and received programmed instructions as mentioned in this paper.
Abstract: A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores a series of first results received from the first calculation circuitry. The rename buffer outputs the series of first results to a first predetermined register. The queue is also coupled to the first calculation circuitry and stores a series of second results. The queue outputs the sequence of second results to a second predetermined register in the same the sequence as it received the second results from the first calculation circuitry.

Patent•
29 Sep 1995
TL;DR: In this paper, the frequency of the spur interference is determined and fed to a notch filter so as to center the notch at the same frequency as the spur, to avoid cancellation of desired periodically repeating components of the signal.
Abstract: EMI spur interference is reduced in a system where the desired signal has periodically repeating components without destructively interfering with the repeating components. The frequency of the spur interference is determined (203) and fed to a notch filter (201) so as to center the notch at the frequency of the spur interference. Determination of the frequency is scheduled (601) to avoid cancellation of desired periodically repeating components of the signal.

Patent•
09 Feb 1995
TL;DR: In this article, a data processing system and a method for performing a snoop-retry protocol using an arbiter is presented, where the arbiter provides simple arbitration support to guarantee the update of the memory has the highest priority among bus masters.
Abstract: A data processing system (10) and method for performing a snoop-retry protocol using an arbiter (14). Multiple bus masters (12, 16, 17) are coupled to multiple shared buses (20, 22, 24, 26). Each bus master (12, 16, 17) may initiate a bus transaction ("initiating master"), or snoop the bus transaction ("snooping bus master") occurring on a shared bus (20). When an initiating processor requests access to a dirty cache line in a memory (18), a snooping bus master asserts a shared address retry (ARTRY*) signal to inform the initiating processor to relinquish ownership of the shared bus (20) and retry the bus transaction. Upon detecting the shared ARTRY* signal, all potential bus masters remove their bus requests and ignore any bus grants from the arbiter (14), thus allowing the snooping processor which asserted the ARTRY* signal to gain ownership of the shared bus (20) to perform the snoop copyback. The arbiter (14) provides simple arbitration support to guarantee the update of the memory (18) has the highest priority among masters ( 12, 16, 17).

Patent•
22 May 1995
TL;DR: In this paper, a method for fabricating a 1-transistor EEPROM device, which can be programmed and erased by Fowler-Nordheim tunneling includes the formation of a memory gate (28) overlying a tunneling region (22), and aligning source and drain regions in a semiconductor substrate (10).
Abstract: A method for fabricating a 1-transistor EEPROM device, which can be programmed and erased by Fowler-Nordheim tunneling includes the formation of a memory gate (28) overlying a tunneling region (22), and aligning source (32) and drain (34) regions in a semiconductor substrate (10), such that a vertically oriented electric field (46) is created in the tunneling region (22). The memory gate (28) is coupled to a contact region (30) by a connecting portion (31). A select gate (14) controls a portion of the channel region in the substrate (10) adjacent to the tunneling region (22). The EEPROM device is programmed by applying a voltage of a first polarity memory gate (28), while applying a voltage of a second polarity to the source region (32), the drain region (34), and to the substrate (10). Under the applied voltages, charge carriers tunnel through a tunnel oxide layer (40) and into a silicon nitride layer (42), located intermediate to the memory gate (28) and the tunnel region (22). To erase the EEPROM device, the polarity of the applied voltages is reversed, and charge carriers of an opposite conductivity type tunnel into the silicon nitride layer (42).