Showing papers by "Freescale Semiconductor published in 1996"

Method for testing a ball grid array semiconductor device and a device for such testing

Abstract: A ball grid array semiconductor device (30) includes a plurality of conductive balls (36) and a plurality of conductive castellations (18) around its periphery as redundant electrical connections to a semiconductor die (12). During testing of the device in a test socket (50), the conductive castellations are contacted by test contacts (54). The test contacts do not come in physical contact with the conductive balls. As a result, when testing is performed at elevated temperatures near the melting point of the conductive balls, the conductive balls are not deformed by the test contacts, thereby eliminating cosmetic-defects. Additionally, the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that conductive balls will inadvertently fuse to the test socket or create solder build-up on the test contacts.

Automatic layout standard cell routing

Abstract: A method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints (1502) and enhancing yield starts with a prerouting step (152) that routes adjacent transistors using diffusion wiring (1506), routes power and ground nets (1508), routes aligned gates (1510), routes all remaining aligned source/drain nets as well as any special nets (1512). Next, all of the remaining nets are routed using an area based router (1408). Nets are order based on time criticality or net topology (1602). A routing grid is assigned for all the layers to be used in routing (1604). An initial coarse routing is performed (1606). Wire groups are assigned to routing layers (1608). Routing is improved and vias are minimized (1610). A determination is then made whether the routing solution is acceptable (1612). If the routintg solution is not acceptable, the routing space is expanded and routing costs and via costs are modifyied to improve the routing solution. Finally, the best routing solution is picked (1414).

Integrated image reject mixer

Abstract: An integrated image reject mixer (150) generates precise quadrature components using highly matched local-oscillator (LO) path and intermediate frequency (IF) path resistor-capacitor (RC) phase shifting networks (131, 138). Because the LO signal from a local oscillator (127) has a constant amplitude, a phase detector (136) feedback loop easily maintains an accurate ninety-degree phase difference between the quadrature LO signals (122, 124) from the LO path phase shifting network (131). Because the two phase shifting networks are matched, the feedback control signal (137) from the phase detector (136) can also be used to maintain an accurate ninety-degree phase difference between the quadrature IF signals (123, 128) from the IF path phase shifting network (138) despite the dynamically-varying amplitude of the IF signal. Thus, this image reject mixer uses only components that may be easily integrated into an integrated circuit.

Electronic component and method of packaging

Abstract: A method of packaging an electronic component includes forming a hole (24) in a substrate (21) having a first surface (22) opposite a second surface (23) and disposing and patterning a malleable layer (26) over the first surface (22) and over the hole (24) of the substrate (21). The malleable layer (26) has a third surface (27) opposite a fourth surface (28). A portion (29) of the fourth surface (28) is exposed by the hole (24) in the substrate (21). An electrically conductive layer is simultaneously disposed over the portion (29) of the fourth surface (28) and over a different portion of the third surface (27) of the malleable layer (26). The malleable layer (26) is deformed into the hole (24). Then, a semiconductor die (43) is coupled to the malleable layer (26), and an underencapsulant (37) is disposed under the semiconductor die (43) and over the hole (24).

Memory cell structure in a magnetic random access memory and a method for fabricating thereof

Abstract: A magnetic random access memory (MRAM) cell structure (10) with a portion of giant magnetoresistive (GMR) material (11), around which single or multiple word line (12) is wound, is provided. Magnetic field generated by word current (13, 14) superimposed in portion of GMR material (11) so that a total strength of magnetic field increases proportionally. The same word current is passed through the portion of GMR material (11) multiple times, thus producing equivalent word field by many times as large word current in a conventional MRAM cell.

LED display packaging with substrate removal and method of fabrication

Abstract: A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer. The light emitted from the LED display chip, being emitted through the remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer of the display chip.

Method of routing an integrated circuit

Abstract: A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.

Method and apparatus for demodulation and power control bit detection in a spread spectrum communication system

Abstract: A receiver circuit (400, 500) receives a spread spectrum communication signal, such as a DS-CDMA signal, including a pilot channel and including a power control designator. The signal is despread and decoded. The pilot symbols on the pilot channel are provided to a channel estimator (408) for estimating the channel phase and channel gain of the communication channel. This estimate is provided to a demodulator (422) for demodulating the traffic channel symbols. The pilot symbols are provided to another channel estimator (410) for estimating channel phase and channel gain for the power control designator. This estimate is provided to a demodulator (424) for demodulating the power control designator. The traffic channel symbols are delayed a predetermined time in a delay element (420) before demodulating. The power control designator is delayed a short time or not at all in a short delay element (418) before demodulation.

Three dimensional semiconductor package having flexible appendages

Abstract: A three dimensional packaging approach reduces the overall footprint for interconnecting multiple semiconductor die. An three-dimensional folded module (10) produces a final package having a footprint size reduced by an approximate factor of four when compared to conventional electronic packaging. The module has a protective covering such as a cap (62) or a sealant (64) as a moisture barrier. Thus, high integration using flexible appendages (15, 25, 35, and 45) attached to a rigid substrate (12) and singularly folded above the substrate (12) results in both a small footprint package and also a light package. A reel-to-reel flex tape (56) assembly provides pre-tested flex boards (16, 26, 36, and 46) resulting in a cost-effective manufacturable package for semiconductor components.

Integrated electro-optical package with independent menu bar

Abstract: An integrated electro-optical package (50) including a first light emitting device (LED) display chip (28) and at least one additional LED display chip (30), each composed of an optically transparent substrate (10) with an array (15) of LEDs (12) formed thereon and cooperating to generate a complete image. The LEDs (12) of the first LED display chip (28) are constructed to emit light of a wavelength different than the light emitted by the additional LED display chip(s) (30), thereby creating a different color menu or object bar (156) within the view (150) generated. A mounting substrate (25), having connection pads (32), bump bonded to the pads on the optically transparent substrate (10). A driver substrate (55) having connections to the pads (32) on the mounting substrate (25). A plurality of driver and control circuits (57) connected to the LED display chips (28) and (30) through electrodes on the driver substrate (55). A lens (73) in alignment with the LED display chips (28) and (30) to magnify the complete images and produce an easily viewable virtual image.

Method of fabricating GMR devices

Abstract: A method of fabricating GMR devices on a CMOS substrate structure with a semiconductor device formed therein. The method includes forming a dielectric system with a planar surface having a roughness in a range of 1 Å to 20 Å RMS on the substrate; disposing and patterning films of giant magneto-resistive material on the planar surface so as to form a memory cell; disposing a dielectric cap on the cell so as to seal the cell and provide a barrier to subsequent operations; forming vias through the dielectric cap and the dielectric system to interconnects of the semiconductor device; forming vias through the dielectric cap to the magnetic memory cell; and depositing a metal system through the vias to the interconnects and to the memory cell.

Method and apparatus for selecting a register file in a data processing system

Abstract: A data processing system selects between a general register file and an alternate register file during an operation such that resources of the data processor may be more flexibly mapped to a context of the data processing system and, therefore, be more efficiently utilized. A control bit in a processor status register (PSR) is used to select between a general register file and an alternate register file depending upon a logic value to which it is set to a during an exception handling process.

Vertically integrated sensor structure and method

Abstract: A vertically integrated sensor structure (60) includes a base substrate (71) and a cap substrate (72) bonded to the base substrate (71). The base substrate (71) includes a transducer (78) for sensing an environmental condition. The cap substrate (72) includes electronic devices (92) formed on one surface to process output signals from the transducer (78). The sensor structure (60) provides an integrated structure that isolates sensitive components from harsh environments.

Metallization and termination process for an integrated circuit chip

Abstract: A process for metallizing an integrated circuit chip to form an interconnecting pattern for the chip's input/output terminals, wherein the process can be performed while the chip is still a part of the wafer on which it is fabricated and before separation into individual chips. The invention uses photodefinable resins as masks that form permanent dielectric layers of a multilayer structure with which interconnecting paths and terminals are defined on the surface of the chip. The process further employs conversion techniques that enable the interconnecting paths to be formed from metals other than aluminum, such that the electrical performance of the chip is enhanced. The use of the photodefinable resins renders the process of this invention conducive to inline processing techniques, thereby reducing processing costs while promoting high throughput and short cycle times. The process of this invention also enables the interconnecting paths to be readily customized for adaption to changing configuration requirements at the next assembly level, while also promoting greater dimensional precision of bumps formed at the terminals.

Method and apparatus for testing an integrated circuit

Abstract: An apparatus and method for laser ablating residue off of probe tips. In one embodiment, the probe tips of the probe needles (16) contact the test pads of an integrated circuit on a wafer (18). The probe tips build up a residue over time. This residue is due to the probe tips coming into contact with integrated circuit wafer layers such as layers (114), (120), (122), (124), and (126). This residue can be vaporized from the surface of the probe needles via exposure to a laser light. The probe needles (16) are exposed to a laser light created by a laser source (28) and ported to the probe tips by a fiber optic cable (26).

Pattern writing method during X-ray mask fabrication

Abstract: A pattern writing method for X-ray mask fabrication including forming a uniform membrane layer on an X-ray absorbing layer and forming an etch mask on the layer of X-ray absorbing material including the steps of providing a layer of material sensitive to radiation. The layer of material has internal stresses which are altered by exposure to the radiation. The material is exposed in associated areas (e.g. a spiral) such that the internal stresses within the layer of material and altered internal stresses in the associated areas are substantially offset to reduce distortion in the X-ray mask.

Method and apparatus for moving data in a parallel processor

Abstract: A method and apparatus for moving data in a parallel processing system (3). In one embodiment, a single instruction accesses one significant bit of information from each element in processing element array (80) and combines these bits into one designated element in global register file (50). The ordering of bits in vectors of global register file (50) associates each bit with an element of processing element array (80). Another single instruction distinguishes significant bit information from a particular vector in global register file (50) and transfers that information to an associated bit in storage circuits associated with each element in processing element array (80).

Magnetic random access memory having stacked memory cells and fabrication method therefor

Abstract: A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).

Pipelined fast-access floating gate memory architecture and method of operation

Abstract: A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Method of selecting a memory cell in a magnetic random access memory device

Abstract: Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell

Circuit and method of controlling mixer linearity

Abstract: An integrated receiver circuit (10) has a first amplifier (12) coupled for receiving a radio frequency (RFIN) input signal. A mixer (16) has an RF input coupled to an output of the first amplifier, a local oscillator (LO) input coupled for receiving an LO signal, and an output for providing an intermediate frequency (IF) signal. A second amplifier (20) has an input coupled for receiving the IF signal, and an output for providing a receive signal strength indicator (RSSI) signal representative of an input power level of the receiver signal path. A feedback circuit (22-26 or 72, 78) is coupled between the first output of the second amplifier and a linearity control input of the mixer for controlling linearity of the mixer.

Method and apparatus for interleaving data in an asymmetric digital subscriber line (ADSL) transmitter

Abstract: In an ADSL transmitter (62), data is flamed and split between a fast path and an interleave path by multiplexer (66) Data is forward error correction encoded in FEC encoder (70) Data on the interleave path is interleaved by interleaver (72) if an interleave depth (D) is >2 During interleaving, at least one additional read operation is performed, after a series of consecutive write and read operations The additional read operation permits interleaving to continue without waiting for a next frame of data to arrive at the interleaver An equal number of additional write operations compensates for the additional reads at a later point Use of an interleaving memory can also be avoided by turning off or disabling the interleaver, while still permitting data to be sent along the interleave path Transmit path controller (74) senses if D=1, and if so disables the interleaver and avoids the need for interleaver memory (64)

Phase locked loop using digital loop filter and digitally controlled oscillator

Abstract: A phase locked loop (10) with a phase detector (11), a digital loop filter (12), a digital controlled oscillator (13) and a divide-by-N circuit (14) generates a periodic signal which has a predetermined phase and voltage related to a reference clock signal. A phase and frequency detector (21) outputs an average of error between a feedback delay clock and a reference clock to the digital loop filter (12). The digital loop filter (12) processes the phase detector (11) output and the inband quantization noise utilizing a sigma delta converter. The digital loop filter (12) utilizes a non binary weight scheme to minimize the number of bits changing states. The digital controlled oscillator (13) generates a loop clock signal utilizing a plurality of digital programmable delay elements. A divide-by-N circuit (14) performs a divide by 2560.

Bonding structure for an electronic device

Abstract: A bonding structure (10) is formed between a first component (12) and a second component (11) to form a semiconductor device. The bonding structure (10) comprises a bump (24) that has a pedestal region (22) and a crown region (23). The crown region (23) is anchored into a well region (13) of a conductive material (16) that is formed on the second component (11).

Data processor with flexible data encryption

Abstract: A data processor (20) which flexibly encrypts data within different address ranges includes an encryption determination circuit (50) to monitor an address conducted on an internal address bus (22) and when the address is within certain predefined ranges, perform encryption or decryption of address and/or data. For example the encryption determination circuit (50) may be used to selectively enable a data encryption-decryption circuit (60). When the data encryption-decryption circuit (60) is disabled, data conducted on an internal data bus (23) becomes "cleartext", i.e., non-encrypted. In one embodiment, the data encryption-decryption is performed in partial dependence on the address itself, and the address conducted to the external address bus is itself selectively encrypted as well.

Dual mode optical Magnifier system

Abstract: A dual mode optical magnifier system (22) including a plurality of multi-order diffractive optical elements (24) having at least one reflective, refractive and conventional diffractive surface formed thereon, that in combination are operable between a low magnification virtual image display mode (26) and a high magnification virtual image display mode (28). The multi-order diffractive optical elements (24) include a plurality of zones defined by P×2π, where P is an integer. The use of multi-order diffractive optical elements (24) enables the elements (24) to be very planar and compact in form so as to be incorporated into portable electronic equipment (40 and 60) such as cellular telephones, pagers, smart card readers (20), computers, or the like, while enabling the desired magnification level to be achieved.

Method of operating a random access memory device having a plurality of pairs of memory cells as the memory device

Abstract: A magnetic random access memory device (10) has a plurality of pairs of memory cells (21a,21b), a column decoder (31), a row decoder (32), and a comparator (60). The pair of memory cells (21a,21b) is designated by column decoder (31) and row decoder (32) in response to a memory address. Complementary bits ("0" and "1") are stored in the pair of memory cells (21a,21b). When the state in the pair of memory cell (21a,21b) is read, both bits in the pair of memory cells (21a,21b) are compared to produce an output at one read cycle time to a bit line (70). This memory device omits a conventional auto-zeroing step so that a high speed MRAM device can be attained.

Lateral MOSFET with modified field plates and damage areas

Abstract: A FET including a channel region and a drift region in a channel layer with a source in the channel region and a drain in the drift region. The current channel between the source and drain defining a straight transistor portion and a curved transistor portion. An oxide with a thin portion overlying the channel region and a thick portion overlying the drift region, and a gate on the thin oxide overlying the current channel. A drain field plate and a gate field plate on the thick oxide with spaced apart edges and a damaged region underlying the edges of the field plates only in the curved transistor portion to reduce electric fields at the edges of the field plates. Also, the current channel has a greater length and the edges are spaced apart farther in the curved transistor portions.

Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride

Abstract: Reflective notching of a photoresist pattern (20), generated over reflective materials on a semiconductor substrate (12), is minimized by using an anti-reflective layer (20) of silicon-rich silicon nitride. The layer of silicon-rich silicon nitride is formed over the reflective materials and a layer of photoresist is then formed over the silicon-rich silicon nitride. The photoresist layer is then photolithographically patterned to form an integrated circuit pattern (20). The silicon-rich silicon nitride layer has an absorptive index of greater than 0.25, which allows it to be used as an anti-reflective layer with photolithographic patterning systems having ultraviolet and deep ultraviolet exposure wavelengths.

Heat dissipation apparatus and method

Abstract: A heat dissipation apparatus (51) has a lid (12) and an optimized fin arrangement (16) located in a cavity (57) of a base (11). Semiconductor chips (41, 42, 43, 44, 45, and 46) are coupled to the lid (12), and a heat conducting medium (47) is forced into the cavity (57) through a port (13) and out of the cavity (57) through a different port (14). Heat generated by the semiconductor chips (41, 42, 43, 44, 45, and 46) is thermally conducted into the fin arrangement (16) and then transferred into the heat conducting medium (47).