Showing papers by "Freescale Semiconductor published in 1997"

Split-gate memory device and method for accessing the same

Abstract: An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).

Low switching field magnetoresistive tunneling junction for high density arrays

Abstract: A low switching field magnetoresistive tunneling junction memory cell including a first exchange coupled structure having a pair of magnetoresistive layers and an exchange interaction layer sandwiched therebetween so as to pin the magnetic vectors of the pair of layers anti-parallel, a second exchange coupled structure having a pair of magnetoresistive layers and an exchange interaction layer sandwiched therebetween so as to pin the magnetic vectors of the pair of layers anti-parallel, and electrically insulating material sandwiched between the first and second exchange coupled structures to form a magnetoresistive tunneling junction. Each of the first and second exchange coupled structures, and hence the memory cell, has no net magnetic moment.

Data processing system for controlling execution of a debug function and method therefor

Abstract: A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unit (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

Rapid thermal processing susceptor

Abstract: A rapid thermal processing susceptor including a base having a planar surface and an upright sidewall extending around a periphery thereof and encircling a working portion of the planar surface. The working portion and the sidewall define a cavity. A plurality of minimum contact points extend from the working portion into the cavity and are positioned to receive thereon a semiconductor wafer. A cover is receivable by the sidewall for enclosing the cavity.

Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits

Abstract: A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned and etched overlying the gate dielectric (14a) whereby the plasma etching of the gate electrode (20) results in substrate plasma damage (22). A post gate wet oxidation process is performed between 750° C. and 850° C. to reduce plasma etch damage and trap sites (16, 18) in order to provide an improved gate dielectric (14b). Source and drain electrodes (30) are then formed within the substrate and laterally adjacent the gate electrode (20) to form a transistor device having more consistent threshold voltages, improved subthreshold slope operation, reduced gate to channel leakage, and improved speed of operation.

Method and apparatus for performing operative testing on an integrated circuit

Abstract: A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built in the corners of the die (5) and connected to the monitor unit (10) via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch (20) in the monitor unit (10). Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system. Other embodiments provide the monitor unit on the die, allowing for later testing and user confirmation.

Data processor with a privileged state firewall and method therefore

Abstract: A data processor (20) includes a firewall circuit (50) that monitors privilege level changes or transitions between privilege modes, such as from user mode and user space into supervisory or privileged mode and operating system space. The firewall circuit starts a timer (54) whenever a central processing unit (22) enters supervisor mode. If the timer (54) determines the passage of a predetermined time while the central processing unit remains continuously in supervisory mode without re-entering user mode, a predefined security policy is invoked. For example, the security policy may require at this point that the data processor (20) is to be reset. Different timer (54) time-out values and different security policies can be set for different types of privilege level changes. In one embodiment, a default time-out value provides protection for multiple types of privilege level changes.

Method for growing an epitaxial layer of material using a high temperature initial growth phase and a low temperature bulk growth phase

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Method of forming a semiconductor device having dual inlaid structure

Abstract: A method for forming semiconductor device (1) that includes providing a substrate (10) having a metal interconnect (12), depositing a via interlevel dielectric (ILD) layer (20) over the substrate (10) and the metal interconnect (12), etching the via ILD layer (20) to form a via (30) over the metal interconnect (12), depositing a trench ILD layer (32) over the via ILD layer (12) and the via (30), etching the trench ILD layer (32) to form a trench (40), the trench (40) being contiguous with the via (12), and depositing a metal (44) so as to fill the via (30) and the trench (40), and provide electrical connection with the metal interconnect (12).

Electronic component assembly having an encapsulation material and method of forming the same

Abstract: An electronic component assembly (10) is formed by mounting an electronic component (31) to a substrate (11). An encapsulating material (33) is used to protect the electronic component (31) from environmental hazards. The encapsulating material (33) is formed by dispensing an encapsulating fluid over the electronic component (31). A trench (36) is formed in a masking layer (21) on a substrate (11) to stop the flow of the encapsulating fluid. The trench (36) provides an edge (35) which acts as a discontinuity in the surface (23) of the masking layer (21). This discontinuity is sufficient to control the flow of the encapsulating fluid until the encapsulating fluid is cured to form the encapsulating material (33).

Multi-layer magnetic random access memory and method for fabricating thereof

Abstract: A new magnetic random access memory (MRAM) unit (30) is provided suitable for fabricating a MRAM device (20). The MRAM cell includes a magnetic storage element (32) and a current control element (33), for example, a diode, connected to the magnetic storage element in series to control a current in the magnetic storage element. The magnetic storage element has two magnetoresistive layers (36,38) separated by a non-magnetic layer (37), for example, aluminum oxide (Al2 O3). The diode allows a current to flow in only an MRAM cell activated by a column line and a row line.

Stray magnetic shielding for a non-volatile MRAM

Abstract: A non-volatile magneto-resistive memory positioned on a semiconductor substrate is shielded from stray magnetic fields by a passivation layer partially or completely surrounding the non-volatile magneto-resistive memory. The passivation layer includes non-conductive ferrite materials, such as Mn--Zn-Ferrite, Ni--Zn-Ferrite, MnFeO, CuFeO, FeO, or NiFeO, for shielding the non-volatile magneto-resistive memory from stray magnetic fields. The non-conductive ferrite materials may also be in the form of a layer which focuses internally generated magnetic fields on the non-volatile magneto-resistive memory to reduce power requirements.

Semiconductor device having a metal containing layer overlying a gate dielectric

Abstract: Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

Method for allocating data in a data communication system

Abstract: A communications system (30) includes a transceiver (42) for transmitting data from a plurality of bins. Specifically, the BER of the bins is substantially equalized by allocating data by determining a projected margin. The projected margin is calculated for each bin by subtracting a reference signal-to-noise value from an estimated bin signal-to-noise value. The reference signal-to-noise value is predetermined by theoretical calculation or empirical data and stored in a look-up table. Bits are allocated to the bin having the maximum projected margin. This provides the best BER without changing the transmit power.

Magnetic device having multi-layer with insulating and conductive layers

Abstract: A magnetic device (40) having multi-layer (41-45) with insulating layer (45) and conductive layer (42). The conductive layer (42) is positioned between a first magnetic layer (41) and a third magnetic layer (44). The insulating layer (45) is positioned between a second magnetic layer (43) and the third magnetic layer (44), and which forms a tunnel junction between the second and third layers. Magnetic vectors in the first magnetic layer (41) magnetically couple with ones in the second magnetic layer (43) so that the magnetic coupling loop formed around the third magnetic layer (44) allows magnetic vectors in the third magnetic layer (44) to be switchable in a low magnetic field. Consequently, total power consumption of the magnetic device (60) decreases.

Ball grid device with optically transmissive coating

Abstract: A semiconductor device (10) coupled to ball grid array substrate (11) and encapsulated by an optically transmissive material (29, 31). The ball grid array substrate (11) has conductive interconnects (14) and a semiconductor receiving area (17) on a top surface and solder pads (13) on a bottom surface. An optoelectronic component (24) is mounted on the semiconductor receiving area (17) and encapsulated with the optically transmissive material (29, 31). Solder balls (18) are formed on the solder pads (13).

Method of testing a semiconductor device by automatically measuring probe tip parameters

Abstract: An integrated probe tip (20) parameter measuring device (70) is integrated onto the chuck (24) or substrate holder of a probe test station (10). Probe tip (20) force can be simultaneously measured for either a single probe tip, several probe, or all of the probe tips on a probe card (18). Integrating the measurement of probe tip (20) parameters such as probe tip force into a test station (10) yields real-time data about the probe process and allows feedback between measured probe tip parameters and probe chuck overdrive in the vertical direction. This integrated testing is done by periodically testing probe tip (20) parameters during the probing of die (26) on a wafer (22).

Method of forming a silicon nitride layer

Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.

Method of making a semiconductor device using chemical-mechanical polishing having a combination-step process

Abstract: A method of chemical-mechanical polishing of a semiconductor device utilizes a combination of polishing steps, including a first step using a first slurry containing an abrasive component (i.e., mechanical component) and a chemical component (i.e., chemical reactants), and a second polishing step using a second slurry having a reduced amount of the abrasive component. The method is carried out with respect to metal (39), such as copper, deposited on a dielectric layer (34) and the first polishing step is stopped before the entirety of the metal overlying the dielectric layer is removed. In one embodiment, the second slurry has no abrasive component.

Method for forming bumps on a substrate

Abstract: Solder bumps are formed on a substrate, such as a semiconductor die (28) or wafer, using a screen printing and reflow operation. Solder paste (18) is screened into openings (14) of a stencil (10). The paste is reflowed within the stencil to produce a solder preform (22). The stencil and solder preforms are then aligned over the substrate to be bumped so that the preform aligns with a metal pad (30) on the substrate. The solder preforms are again reflowed, and the solder within the openings of the stencil is drawn onto the metal pad. To facilitate the transfer of the solder from the stencil to the metal pad, a second stencil (12) can be used to form a protrusion (27) on the solder preform. The protrusion contacts the metal pad during the transfer reflow operation to facilitate removing the solder from the stencil.

Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same

Abstract: A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.

Method for fabricating a semiconductor device using lateral gettering

Abstract: A semiconductor structure (20) includes a silicon layer (16) formed on an oxide layer (14) Gettering sinks (31, 32) are formed in the silicon layer (16) Lateral gettering is performed to effectively remove impurities from a first section (26) of the semiconductor layer (16) An insulated gate semiconductor device (40) is then formed in semiconductor layer (16), wherein a channel region (55) of the device (40) is formed in the first section (26) of the semiconductor layer (16) A gate dielectric layer (42) of the device (40) is formed over a portion of the first section (26) after the lateral gettering process, thereby enhancing the integrity of the gate dielectric layer (42)

Integrated circuit memory using fusible links in a scan chain

Abstract: An integrated circuit memory (140) includes programmable fuses (20) coupled to scannable flip-flops (25). The programmable fuses (20) and scannable flip-flops (25) are implemented in a scan chain, and are used to program specific information about the integrated circuit memory (140), such as for example, repair (redundancy) information, wafer lot number and wafer number, die position on the wafer, or any other information that would be useful during or after package testing.

Monolithic RF mixed signal IC with power amplification

Abstract: A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).

Magnetic memory cell with increased GMR ratio

Abstract: First and second layers of magnetic material are stacked in parallel, overlying relationship and separated by a first layer of non-magnetic material sandwiched therebetween to form a magnetic memory cell. A layer of oxide (e.g. NiO) is positioned on either one or both major surfaces of the magnetic memory cell. The oxide has a thickness (e.g. less than approximately 150 Å) which prevents the layer of oxide from pinning the first and second layers of magnetic material and adapts the layer of oxide to the first and second layers of magnetic material so as to increase the GMR ratio of the magnetic memory cell.

Method of chemical mechanical planarization using copper coordinating ligands

Abstract: A method of CMP of the semiconductor device where the method comprises the sequential steps of providing a semiconductor device, forming a copper layer on the semiconductor device and planarizing the copper layer with a medium. The medium comprises an abrasive component and a chemical solution. The chemical solution comprises water, an oxidizing agent, a first coordinating ligand adapted to form a complex with Cu(I) and a second coordinating ligand adapted to form a complex with Cu(II).

MRAM cell requiring low switching field

Abstract: A low switching field multi-state, multi-layer magnetic memory cell (10) including two layers of magnetic material (23, 24) stacked in parallel, overlying relationship and separated by a layer of non-magnetic material (12) so as to form a portion of a multi-layer magnetic memory cell. The two layers of magnetic material being formed so that the width is less than the length and less than a width of magnetic domain walls within the two layers of magnetic material, setting a shape anisotropy easy axis along the length thereof. At least one of the two layers of magnetic material having a magnetic anisotropy generally parallel to the width of the layers of magnetic material.

Method and data processing system for dynamically accessing both big-endian and little-endian storage schemes

Abstract: A method and apparatus is used to allow big-endian data and little-endian data to be read from memory in a dynamic manner. A multiplexer controller (18) is provided size bits and two low order address bits A0 and A1 as control signals from a CPU (16). A0 is used by the controller (18) to distinguish between little-endian reads and big-endian reads for both 16-bit halfword accesses and 32-bit word accesses. Using the control signals from the CPU (16), the controller (18) provides ten control signals to a multiplexer 20. One of signals A-D are enabled for byte accesses, one of signals E'-G' are enabled for big-endian halfword or word accesses, and one of the signals E"-G" are enabled for little-endian halfword or word accesses. The multiplexor switches the external data from big-endian or little-endian to a common CPU-internal format while also aligning data reads for byte and halfword accesses in response to the ten control signals.

Angular velocity sensor

Abstract: Converting a Coriolis force into an electrical signal, an electro-mechanical transducer (10) is a field effect transistor (18) having angular velocity sensing capabilities. A gate electrode (16) is suspended over a channel region (60) of a substrate (31), is biased at a desired potential, and is oscillated along an axis (40). The gate electrode (16) and the substrate (31) are rotated about a different axis (41) at an angular velocity (44). The resulting Coriolis force displaces the suspended gate electrode (16) along yet another axis (42) which modulates a current (53) in the channel region (60) of the substrate (31). The amplitude of the current (53) describes the magnitude of the angular velocity (44).

Material transfer apparatus and method of using the same

Abstract: A material (21) is transferred to an electronic component (32) using a transfer apparatus (10). The transfer apparatus (10) has pins (13) that pass through openings (19) in a cavity plate (16). The pins (13) and the openings (19) in the cavity plate (16) form cavities (20) that are filled with the material (21). The pins (13) are then extended from the cavity plate (16) to transfer the material (21) from the cavities (20) to the electronic component (32).