Showing papers by "Freescale Semiconductor published in 2000"

Magnetic random access memory and fabricating method thereof

Abstract: An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

Micro-electromechanical system device

Abstract: A Micro-Electromechanical Systems (MEMS) device (100) having conductively filled vias (141). A MEMS component (124) is formed on a substrate (110). The substrate has conductively filled vias (140) extending therethrough. The MEMS component (124) is electrically coupled to the conductively filled vias (140). The MEMS component (124) is covered by a protective cap (150). An electrical interconnect (130) is formed on a bottom surface of the substrate (110) for transmission of electrical signals to the MEMS component (124), rather than using wirebonds.

UV cure process and tool for low k film formation

Abstract: A process and system for forming a low dielectric film in a semiconductor fabrication process are disclosed. Initially, a carbon-doped silicon oxide film is deposited on a semiconductor wafer. Light energy, such as ultraviolet (UV) energy, is then applied to the deposited film to cure the film. In one embodiment, at least 30% of the light energy is at a frequency greater than that of visible light. In the preferred embodiment, the application of the light energy to the wafer does not significantly heat the wafer. The invention further contemplates a cluster tool or system suitable for forming and curing the dielectric film. The cluster tool includes a first chamber coupled to an organosilane source, a second chamber configured to apply light energy to a wafer received in the second chamber, and a robotic section suitable for controlling movement of wafers between the first chamber and the second chamber.

System and method for baseband removal of narrowband interference in ultra wideband signals

Abstract: A system, method, and computer program product for baseband removal of narrowband interference contained within UWB signals in a UWB receiver. The RFI is extracted from the UWB signal by employing a filter that is matched approximately with the RFI in the baseband signal, extracting RFI, and passing the desired data signal unscathed.

Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation

Abstract: A microprocessor architecture (310) has a plurality of functional units arranged in a parallel manner between one or more source buses (412 and/or 414) and one or more result buses (490). At least one of the functional units within the architecture is a content addressable memory (CAM) functional unit (430) which can be issued CPU instructions via a sequencer (480) much like any other functional unit. The operation of the CAM (430) may be pipelined in one or more stages so that the CAM's throughput may be increased to accommodate the higher clock rates that are likely used within the architecture (310). One embodiment involves pipelining the CAM operation in three stages (510, 520, and 530) in order to sequentially perform data input and precharge operations, followed by match operations, and followed Finally by priority encoding and data output.

Memory cell and method for programming thereof

Abstract: A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).

Process for forming a high-K gate dielectric

Abstract: A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO2 or a combination of SiO2, SiO3 and SiO4 (oxide-nitride or oxynitride) stacks.

Digital predistortion for amplifiers

Abstract: A method for predistorting a digital signal prior to amplification is disclosed in which a look-up table is computed using power values of digital input signal samples as look-up values. The look-up table is preferably a function of pre-measured calibration data. The look-up table is applied to digital input signals for producing the predistorted signal. Computing the look-up table may include determining a set of input power values, obtaining the pre-measured calibration data including an output power data value and phase data value of the amplifier corresponding to each of the input power values, and deriving a set of calibration power values using the output power data values. The calibration power values and the input power values are then used to derive amplitude predistortion calibration values while the phase data values are used to determine phase predistortion calibration values. The calibration power values and corresponding amplitude predistortion calibration values are interpolated to provide amplitude predistortion values while the calibration power values and corresponding phase predistortion calibration values are interpolated to provide phase predistortion values. The look-up table is computed from the amplitude predistortion values and the phase predistortion values.

Reconfigurable systems using hybrid integrated circuits with optical ports

Abstract: A hybrid integrated circuit is provided that has a monocrystalline substrate such as silicon and a compound semiconductor layer such as gallium arsenide or indium phosphide An optical communications port may be formed on the hybrid integrated circuit Electrical equipment may be provided that includes electrical components At least a given one of the components may be a hybrid integrated circuit Data used for the operation of one of the given integrated circuit may be provided to the given integrated circuit through the optical communications port on that integrated circuit The data may be loaded rapidly in real time due to the wide bandwidth of the optical communications port

Method for forming a copper layer over a semiconductor wafer

Abstract: A method for electroplating a copper layer (118) over a wafer (20) powers a cathode of an electroplating system (10) in a manner that obtains improved copper interconnects. A control system (34) powers the cathode of the system (10) with a mix of two or more of: (i) positive low-powered DC cycles (201 or 254); (ii) positive high-powered DC cycles (256 or 310); (iii) low-powered, pulsed, positive-power cycles (306 or 530); (iv) high-powered, pulsed, positive-powered cycles (212, 252, 302, or 352); and/or (v) negative pulsed cycles (214, 304, 510, 528, or 532). The collection of these cycles functions to electroplate copper or a like metal (118) onto the wafer (20). During electroplating, insitu process control and/or endpointing (506, 512, or 520) is performed to further improve the resulting copper interconnect.

Magnetic random access memory array divided into a plurality of memory banks

Abstract: An MRAM device has a new type of memory bank ( 10 ) that includes bit lines ( 21-24 ), a reference line ( 27 ) and digit lines ( 25, 26 ), on intersections of bit lines and digit lines a plurality of magnetic memory cells ( 15-18 ) are arrayed. Bit lines are formed on both sides of the reference line on a substrate. Since each bit line is fabricated closely to the reference line, each cell has substantially the same hysteresis characteristics, which allow the MRAM device to provide a steady operation mode.

Method of interconnecting an embedded integrated circuit

Abstract: A method of interconnecting electrical terminations ( 12 ) of an integrated circuit die ( 30 ) to corresponding circuit traces ( 22 ) of a circuit carrying substrate ( 20 ). The die is placed in a cavity ( 24 ) in the substrate such that the electrical terminations on the die are aligned with corresponding circuit traces on the substrate, and so that the surfaces of the die and substrate are coplanar. A film ( 40 ) is vacuum laminated over the substrate and the die with heat and pressure. The film is then heated so that it flows to fill the spaces ( 34 ) between the die and sidewalls of the cavity, and is then cured. Excess film is then removed everywhere except that which is in the space between the die and the cavity walls. Electrical interconnections ( 100 ) are then plated up between the terminations and the circuit traces to bridge the distance between the terminations and the circuit traces. These interconnections are plated directly on the surface of those portions of the laminated film that lie between the sides of the die and of the cavity.

Method of manufacturing vertical semiconductor device

Abstract: An n-channel device (10) and a p-channel device (11) are formed from a single epitaxial silicon layer (60,61). During the deposition of the single epitaxial silicon layer (60,61), dopants are added to the epitaxial reaction chamber and subsequently changed to define a drain region (24,33), a channel region (27,34), and a source region (30,35). The dopant concentration is modified during the formation of the channel region (27,34) to create a doping profile (50). The doping profile (50) has a first profile (51) that is constant and a second profile (52) that changes.

Memory device and method for using prefabricated isolated storage elements

Abstract: A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).

System and method for generating ultra wideband pulses

Abstract: An ultra-wide band (UWB) waveform generator and encoder for use in a UWB digital communication system. The UWB waveform is made up of a sequence of shaped wavelets. The waveform generator produces multi-amplitude, multi-phase wavelets that are time-constrained, zero mean, and can be orthogonal in phase, yet still have a −10 dB power spectral bandwidth that is larger than the frequency of the peak of the power spectrum In one embodiment, the wavelets are bi-phase wavelets. The encoder multiplies each data bit by an n-bit identifying code, (e.g., a user code), resulting in a group of wavelets corresponding to each data bit. The identifying codeword is passed onto the UWB waveform generator for generation of a UWB waveform that can be transmitted via an antenna.

Single instruction for multiple loops

Abstract: Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple loop constructs, such as, for example, nested loops, to achieve improved performance during loop execution. One embodiment contemplates a single instruction that provides for execution of other instructions of a set of instructions in accordance with multiple looping constructs. Another embodiment contemplates a single-loop instruction suitable for terminating on multiple termination conditions.

Process for forming an electrical device

Abstract: The present invention includes a process for forming an electrical device. In one embodiment, the process includes applying a solid patternable film over a substrate and forming a conductive material over the substrate while the solid patternable film overlies the substrate, wherein the conductive material extends at least partially within an opening in the patternable film. In another embodiment, the process includes applying a patterned film over a substrate having a pad and exposing the patterned film and the substrate to energy. The patterned film includes a first region that includes a conductor and a second region that does not have a conductor. The energy of the exposure forms an electrical connection between the conductor and the pad. In yet another embodiment, the process includes mechanically applying a film over a semiconductor device substrate, patterning the film to define a first opening to expose a conductive region within the semiconductor device substrate, forming a first conductive layer within the first opening, and forming a second conductive layer over the first conductive layer.

Ultrawide bandwidth system and method for fast synchronization using multiple detection arms

Abstract: A system and method for fast synchronization of an incoming signal with a UWB receiver rapidly. The present invention synchronizes with a UWB receiver with an incoming signal. The present invention correlates a local pulse generated at the receiver with the incoming signal, finds a phase angle in the correlation function that would correspond to a high signal to noise ratio, thereby matching the receiver to the incoming signal phase, and operates the receiver at that phase. Exemplary options of fast synchronization include using multiple detection arms to compare one parameter of the correlation function to a predetermined threshold.

Non-volatile memory, method of manufacture, and method of programming

Abstract: A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. P-well regions of the array are spaced apart and electrically isolated by shallow trench features. The cells of each column are positioned within a respective isolated p-well region. Control gates of sequentially corresponding memory cells in columns of the array are electrically coupled by common wordlines. Bitlines electrically couple drain regions of each memory cell in the respective columns of the memory cell array. Source lines electrically couple source regions of each memory cell in the respective columns of the array. The source lines and at least one memory cell in each column of the array are electrically coupled to the p-well region corresponding to the column of the source line and cell. Each column of the array is therefore located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials as to each column, with isolation of results for each column.

Fast training of equalizers in discrete multi-tone (DMT) systems

Abstract: A method for fast training of equalizers in a DMT system begins by normalizing the incoming receive signal ( y ) via steps (108-116). By normalizing the signal, the convergence rate of the training algorithm becomes relatively independent of channel line length so that long line lengths may converge to optimal equalizer coefficients in short time periods. The method also iteratively adjusts the filter coefficients w over time by using an adaptive gain vector µ that is updated on a component-by-component basis on each iteration via steps (114-146). By allowing each component of the vector µ to iteratively adapt independent of all other components in the vector µ based upon the binary sign bit of both real and imaginary components of frequency domain gradient vectors G , a convergence to optimal equalizer filter coefficients will occur in a short period of time.

Semiconductor structure having a crystalline alkaline earth metal silicon nitride/oxide interface with silicon

Abstract: A semiconductor structure comprises a silicon substrate (10), one or more layers of single crystal oxides or nitrides (26), and an interface (14) between the silicon substrate and the one or more layers of single crystal oxides or nitrides, the interface manufactured with a crystalline material which matches the lattice constant of silicon The interface comprises an atomic layer of silicon, nitrogen, and a metal in the form MSiN2, where M is a metal In a second embodiment, the interface comprises an atomic layer of silicon, a metal, and a mixture of nitrogen and oxygen in the form MSi[N1-xOx]2, where M is a metal and X is 0≤X<1

Ultra wideband communication system, method, and device with low noise reception

Abstract: An ultra-wide band (UWB) waveform receiver with noise cancellation for use in a UWB digital communication system. The UWB receiver uses a two-stage mixing approach to cancel noise and bias in the receiver. Self-jamming is prevented by inverting a portion of the received signal in the first mixer and then coherently detecting the partially and synchronously inverted signal in the second mixer. Since the drive signals on both mixers are not matched to the desired signal, leakage of either drive signal does not jam the desired signal preventing the receiver from detecting and decoding a weak signal.

Method of identifying an improved configuration for a communication system using coding gain and an apparatus therefor

Abstract: Coding gain is used to configure a communication system using a programmable error correction scheme. A best available error correction configuration is selected from among several configurations to provide an optimal coding gain performance for a given line or set of line characteristics and a given communication system. Payload is calculated for each of several error correction configurations, and the configuration providing the highest payload for a target bit error rate is selected. Use of gross gain to configure the communication system further provides an optimal configuration.

Circuit for generating hash values

Abstract: A Message Digest Hardware Accelerator (MDHA) 10 for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file (12) is initialized to different data values. A function circuit (22) performs logical operations based on the selected algorithm and provides a data value to a summing circuit (30) that is summed with mode dependent constant values selected from registers (34 and 36), round and step dependent data words generated by a register array block (32) to calculate the hash value for a text message stored in registers (100–115).

Process for forming a structure

Abstract: A finished structure ( 100 ) includes a semiconductive region ( 102 ), a first oxide layer ( 106 ), a second oxide layer ( 108 ), and a conductive layer ( 110 ). The first oxide layer ( 106 ) lies between the semiconductive region ( 102 ) and the second oxide layer ( 108 ); and the second oxide layer ( 108 ) lies between the first oxide layer ( 106 ) and the conductive layer ( 110 ). The first oxide layer ( 106 ) includes at least a portion that is amorphous or includes a first element, a second element, and a third element. In the latter, the first element is a metallic element, and each of the first, second, and third elements are different from each other. A process for forming a structure ( 100 ) includes forming a first layer ( 106 ) near a semiconductive region ( 102 ), forming a second layer ( 108 ) after forming the first layer ( 106 ), and forming a third layer ( 110 ) after forming the second layer ( 108 ). The first oxide layer ( 106 ) includes a metallic element and oxygen. The third layer ( 110 ) is a non-insulating layer.

Sensor and method of use

Abstract: A sensor has an electrode (120) that is movable along three mutually perpendicular axes (10, 11, 12). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (120) along the three axes (10, 11, 12).

Mismatch modeling tool

Abstract: A mismatch modeling tool ( 10 ) comprises a software implemented mismatch model ( 32 ) The software implemented mismatch model ( 32 ) accesses: at least one editable mismatch model data library ( 18 ) comprising process parameter variables, and circuit simulation library and program ( 14 ) data output An interface screen ( 100 ) provides input and output coupling between a user and the software implemented mismatch model ( 32 )

Method and apparatus for producing a pulse width modulated signal

Abstract: A method and apparatus to produce a pulse width modulated (PWM) signal from pulse code modulated (PCM) data. In one embodiment, a crossing point of an analog signal with the ramp portion of a sawtooth waveform is approximated by first extrapolating, or projecting, a line between two adjacent sample points across other sample points to produce an estimate of the crossing point. A magnitude difference between a crossing point of the extrapolated line and a sample point magnitude on each side of the crossing point is determined. The magnitude difference, multiplied by an empirically determined constant, is added to the estimate. A PWM signal is then produced using the estimate for the crossing point.

Multiple voltage compatible I/O buffer

Abstract: Input and output buffer circuitry ( 12, 14, 16 ) is provided which are compatible with busses operating at different voltage levels. The buffer circuitry is self-configuring based on the type of bus to which it is coupled. The buffer circuitry includes voltage level detect circuitry ( 20 ) and pad level detect circuitry ( 28 ) which can reconfigure driver ( 34, 54 ) and level shifter circuits ( 24, 26 ) in order to protect the switching devices of the buffers.