Showing papers by "Freescale Semiconductor published in 2004"

Method for treating a semiconductor surface to form a metal-containing layer

Abstract: A method for treating a semiconductor surface to form a metal-containing layer includes providing a semiconductor substrate having an exposed surface. The exposed surface of the semiconductor substrate is treated by forming one or more metals overlying the semiconductor substrate but not completely covering the exposed surface of the semiconductor substrate. The one or more metals enhance nucleation for subsequent material growth. A metal-containing layer is formed on the exposed surface of the semiconductor substrate that has been treated. The treatment of the exposed surface of the semiconductor substrate assists the metal-containing layer to coalesce. In one embodiment, treatment of the exposed surface to enhance nucleation may be performed by spin-coating, atomic layer deposition (ALD), physical layer deposition (PVD), electroplating, or electroless plating. The one or more metals used to treat the exposed surface may include any rare earth or transition metal, such as, for example, hafnium, lanthanum, etc.

Circuit device with at least partial packaging and method for forming

Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

Impact of Deposition and Annealing Temperature on Material and Electrical Characteristics of ALD HfO2

Abstract: Hafnium oxide is one of the most promising high-k materials to replace as a gate dielectric. Here we report material and electrical characterization of atomic layer deposition (ALD) hafnium oxide and the correlations between the results. The films were deposited at 200, 300, or 370°C and annealed in a nitrogen ambient at 550, 800, and 900°C. Results indicate that deposition temperature controls both the material and the electrical properties. Materials and electrical properties of films deposited at 200°C are most affected by annealing conditions compared to films deposited at higher temperatures. These films are amorphous as deposited and become polycrystalline after 800°C anneals. Voids are observed after a 900°C anneal for the 200°C deposited films. The 200°C deposited films have charge trapping and high leakage current following anneals at 900°C. The 300°C deposited films have lower chlorine content and remain void-free following high-temperature anneals. These films show a thickness-dependent crystal structure. Annealing the films reduces leakage current by four orders of magnitude. Finally, films deposited at 370°C have the highest density, contain the least amount of impurities, and contain more of the monoclinic phase of than those deposited at 300 and 200°C. The best electrical performance was obtained for films deposited at 370°C. © 2004 The Electrochemical Society. All rights reserved.

Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Single proof mass, 3 axis mems transducer

Abstract: A transducer is provided herein which comprises an unbalanced proof mass (51), and which is adapted to sense acceleration in at least two mutually orthogonal directions. The proof mass (51) has first (65) and second (67) opposing sides that are of unequal mass.

Buck or boost tracking power converter

Abstract: A cascade of buck and boost converter is presented here. The control operates in a manner that the converter is either in buck or boost (BOB) mode on a cycle by cycle basis. It transitions between the modes seamlessly to provide a tracking power conversion function for modulating the power supply of a variable envelope radio frequency (RF) power amplifier. The control algorithm and its implementation using switched capacitor circuits is described. Simulation and measured experimental results including converter efficiency, tracking accuracy, and spectrum at the output of the RF power amplifier are provided. This control technique allows seamless transition between the buck and boost modes while tracking RF envelopes with bandwidth greater than 100 kHz, and maintaining extreme accuracy and extremely low ripple. The efficiency of this converter operating at 1.68 MHz is close to 90% over a wide range of conversion ratios. The area of the power converter is extremely small allowing this to be integrated into a cellular telephone. The controller was integrated as part of a larger power management IC as well as a discrete IC.

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)

Abstract: Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.

Transistor having three electronically isolated electrodes and method of formation

Abstract: A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters (143, 144), adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

Ultra-thin die and method of fabricating same

Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

Magnetic tunnel junction element structures and methods for fabricating the same

Abstract: Magnetic tunnel junction ('MTJ') element structures and methods for fabricating MTJ element structures are provided. An MTJ element structure (10) may comprise a crystalline pinned layer (26), an amorphous fixed layer (30), and a coupling layer (28) disposed between the crystalline pinned layer and the amorphous fixed layer. The amorphous fixed layer (30) is antiferromagnetically coupled to the crystalline pinned layer (26). The MTJ element further comprises a free layer (34) and a tunnel barrier layer (32) disposed between the amorphous fixed layer and the free layer. Another MTJ element structure (60) may comprise a pinned layer (26), a fixed layer (30) and a non-magnetic coupling layer (28) disposed therebetween. A tunnel barrier layer (32) is disposed between the fixed layer (30) and a free layer (34). An interface layer (62) is disposed adjacent the tunnel barrier (32) layer and a layer of amorphous material (30). The first interface layer (62) comprises a material having a spin polarization that is higher than that of the amorphous material (30).

Die encapsulation using a porous carrier

Abstract: A process for encapsulating an integrated circuit die (403) using a porous carrier (101). In one example, an adhesive structure (e.g. tape) is applied to a porous carrier. Integrated circuit die is then placed on the adhesive structure. The integrated circuit die is then encapsulated to form an encapsulated structure (505). The carrier is then subjected to a solvent that passes through the carrier to reduce the adhesive strength of the adhesive structure for removal of the carrier from the encapsulated structure.

State retention within a data processing system

Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Flip-chip assembley with thin underfill and thick solder mask

Abstract: The invention provides a method for attaching a flip chip (210) to an electrical substrate (240) such as a printed wiring board. A bumped flip chip is provided, the flip chip including an active surface and a plurality of connective bumps (220) extending from the active surface, each connective bump including a side region. A thin layer of an underfill material (230) is applied to the active surface of the flip chip and to a portion of the side regions of the connective bumps. The flip chip is positioned on the electrical substrate, the electrical substrate including a thick layer of a solder mask (250) disposed on the electrical substrate. The flip chip is heated to electrically connect the flip chip to the electrical substrate, wherein the underfill material and the solder mask combine to form a stress-relief layer when the flip chip is electrically connected to the electrical substrate.

Method of forming a nanocluster charge storage device

Abstract: A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters (24). The stack includes a first-formed polysilicon-nitride layer (126) and a second-formed polysilicon-containing layer (28). The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer (28). A top portion of the device is protected from oxidation. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.

Semiconductor device structure and method therefor

Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

On correlating structural tests with functional tests for speed binning of high performance design

Abstract: The use of functional vectors has been an industry standard for speed binning purposes of high performance ICs. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target performance related faults in a more systematic manner. To make structural testing an effective alternative to functional testing for speed binning, structural patterns need to correlate with functional test frequencies closely. We investigate the correlation between functional test frequency and that of various types of structural patterns on MPC7455, a Motorola processor executing to the PowerPC/spl trade/ instruction set architecture.

Method and system for dynamic aggregation in a wireless network

Abstract: A method is provided for dynamically controlling aggregation in an ultrawide bandwidth wireless device. In this method, a device receives a plurality of intermediate service data units at an intermediate layer, aggregates at least two of the plurality off intermediate service data units to form an intermediate protocol data unit, and sends the intermediate protocol data unit to a physical layer. The physical layer generates a data frame based on the intermediate protocol data unit and information corresponding to the physical layer, and transmits the data frame in a data stream. The device selects an intermediate size criteria for the intermediate protocol data unit based on a desired frame size criteria for the data frame. The aggregating of the at least two of the plurality of intermediate layer service data units is performed such that an actual intermediate layer protocol data unit size corresponds to the intermediate size criteria.

Challenges for the integration of metal gate electrodes

Abstract: Integration challenges for metal gate electrodes including the presence of Fermi level pinning and the impact of interface chemistry on the effective metal work function are discussed Gate stack thermal instabilities are explored, and for the first time results using tantalum-carbon based electrodes are presented

Multi-bit non-volatile memory device and method therefor

Abstract: A multi-bit non-volatile memory device includes a charge storage layer (14) sandwiched between two insulating layers (12 and 16) formed on a semiconductor substrate (10). A thick oxide layer (18) is formed over the charge storage layer (14) and a minimum feature sized hole is etched in the thick oxide layer (18). An opening is formed in the thick oxide layer (18). Side-wall spacers (60) formed on the inside wall of the hole over the charge storage layer have a void (62) between them that is less than the minimum feature size. The side-wall spacers (60) function to mask portions of the charge storage layer (14), when the charge storage layer is etched away, to form the two separate charge storage regions (55 and 57) under the side-wall spacers (60). The device can be manufactured using only one mask step. Separating the charge storage regions prevents lateral conduction of charge in the nitride.

Optimized reference voltage generation using switched capacitor scaling for data converters

Abstract: An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

Common signalling mode for use with multiple wireless formats

Abstract: A method is provided for operating a wireless local device In this method a local device receives a beacon for a current superframe in a common signal format The beacon includes time slot assignment information The local device then determines a device format for the transmission of data to a remote device based on format determination information The device format can be one of a common signal format, and one or more wireless formats The local device then determines one or more remote device time slots in the superframe assigned for transmission of the data to the remote device based on the time slot assignment information Finally, the local device transmits the data in the one or more remote device time slots to the remote device using the device format

Semiconductor fabrication process including source/drain recessing and filling

Abstract: A semiconductor fabrication process includes forming a gate dielectric overlying a silicon substrate and forming a gate electrode overlying the gate dielectric. Source/drain recesses are then formed in the substrate on either side of the gate electrode using an NH4OH-based wet etch. A silicon-bearing semiconductor compound is then formed epitaxially to fill the source/drain recesses and thereby create source/drain structures. Exposed dielectric on the substrate upper surface may be removed using an HF dip prior to forming the source/drain recesses. Preferably, the NH4OH solution has an NH4OH concentration of less than approximately 0.5% and is maintained a temperature in the range of approximately 20 to 35° C. The silicon-bearing epitaxial compound may be silicon germanium for PMOS transistor or silicon carbide for NMOS transistors. A silicon dry etch process may be performed prior to the NH4OH wet etch to remove a surface portion of the source/drain regions.

Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices

Abstract: A complementary metal-oxide-semiconductor field effect transistor structure includes ion implants in only one of the two complementary devices. The transistor structure generally includes a compound semiconductor substrate and an epitaxial layer structure that includes one or more donor layers that establish a conductivity type for the epitaxial layer structure. The ion implants function to “invert” or “reverse” the conductivity type of the epitaxial layer structure in one of the complementary devices. In the example embodiment, p-type acceptor implants are utilized in the p-channel device, while the n-channel device remains implant-free.

Hydrogen plasma enhancement of boron activation in shallow junctions

Abstract: The ability to activate large concentrations of boron at lower temperatures is a persistent contingency in the continual drive for device scaling in Si microelectronics. We report on our experimental observations offering evidence for enhancement of electrical activation of implanted boron dopant in the presence of atomic hydrogen in silicon. This increased electrical activity of boron at lower anneal temperature is attributed to the creation of vacancies in the boron-implanted region, lattice-relaxation caused by the presence of atomic hydrogen, and the effect of atomic hydrogen on boron-interstitial cluster formation.

Land grid array packaged device and method of forming same

Abstract: A method of packaging an integrated circuit die (12) includes the steps of providing a foil sheet (30) and forming a layer of solder (32) on a first side of the foil sheet. A first side of the integrated circuit die is attached to the solder on the foil sheet. The first side of the die has a layer of metal (34) on it and a second, opposing side of the die includes bonding pads (14). The bonding pads are electrically connected to the solder on the foil sheet with wires (16). The die, the electrical connections, and the first side of the foil sheet are encapsulated with a mold compound (20). The foil sheet is separated from the die and the wires, which forms a packaged integrated circuit (10).

Memory having variable refresh control and method therefor

Abstract: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

Scribe street structure for backend interconnect semiconductor wafer integration

Abstract: A method of making a semiconductor device includes forming a wafer having a substrate and an interconnect structure over the substrate. The wafer also includes a plurality of die areas and a street located between a first die area of the plurality and a second die area of the plurality. A separation structure that includes metal is located in the interconnect structure. At least a portion of the separation structure is located in a saw kerf of the street. The separation structure is arranged to provide a predefined separation path for separating the first die area during a singulation process.

Semiconductor package having optimized wire bond positioning

Abstract: Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.

Low rc product transistors in soi semiconductor process

Abstract: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

Packaged ic using insulated wire

Abstract: A packaged IC including insulated wire for electrically connecting conductive structures of the packaged IC. In some embodiments, the packaged IC includes an IC die attached to a package substrate, where bond pads of the IC die are electrically connected to bond fingers of the substrate with insulated wire. The insulated wire has a conductive core and an insulator coating. In some examples, the insulator coating includes an inorganic covalently-bonded substance that is not an oxide of the electrically conductive core such as, e.g., silicon nitride or silicon oxide. In one example, the insulator coating is applied to a conductive core by a chemical vapor deposition (CVD) process such as a plasma enhanced chemical vapor deposition (PECVD).