Showing papers by "Freescale Semiconductor published in 2005"

A 4-Mb toggle MRAM based on a novel bit and switching method

Abstract: A 4-Mb magnetoresistive random access memory (MRAM) with a novel magnetic bit cell and toggle switching mode is presented. The circuit was designed in a five level metal, 0.18-mum complementary metal-oxide-semiconductor process with a bit cell size of 1.55 mum2. The new bit cell uses a balanced synthetic antiferromagnetic free layer and a phased write pulse sequence to provide robust switching performance with immunity from half-select disturbs. This switching mode greatly improves the operational performance of the MRAM as compared to conventional MRAM. A detailed description of this 4-Mb toggle MRAM is presented

Toward a Universal Memory

Abstract: Today9s electronic gadgets, such as digital cameras and mp3 players, often contain three different types of memory, because none of these memory types-static random access memory, dynamic random access memory, and Flash-can fulfill all memory requirements of these devices In his Perspective, A…kerman discusses magnetoresistive random access memory (MRAM), a promising candidate for a "universal memory" that combines all the strengths and none of the weaknesses of the existing memory types Several companies have succeeded in creating multi-megabyte MRAM prototypes, suggesting that large-scale introduction of MRAM devices to the market is not far off

Phase-locking in double-point-contact spin-transfer devices

Abstract: Spin-transfer in nanometre-scale magnetic devices results from the torque on a ferromagnet owing to its interaction with a spin-polarized current and the electrons' spin angular momentum. Experiments have detected either a reversal or high-frequency (GHz) steady-state precession of the magnetization in giant magnetoresistance spin valves and magnetic tunnel junctions with current densities of more than 10(7) A cm(-2). Spin-transfer devices may enable high-density, low-power magnetic random access memory or direct-current-driven nanometre-sized microwave oscillators. Here we show that the magnetization oscillations induced by spin-transfer in two 80-nm-diameter giant-magnetoresistance point contacts in close proximity to each other can phase-lock into a single resonance over a frequency range from approximately 24 GHz for contact spacings of less than about approximately 200 nm. The output power from these contact pairs with small spacing is approximately twice the total power from more widely spaced (approximately 400 nm and greater) contact pairs that undergo separate resonances, indicating that the closely spaced pairs are phase-locked with zero phase shift. Phase-locking may enable control of large arrays of coupled spin-transfer devices with increased power output for microwave oscillator applications.

On-chip antennas in silicon ICs and their application

Abstract: The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable This technology can potentially be applied for implementation of a true single-chip radio for general purpose communication, on-chip and inter-chip data communication systems, RFID tags, RF sensors/radars, and others

Multimillimetre-large superlattices of air-stable iron–cobalt nanoparticles

Abstract: Self-organization of nanoparticles into two- and three-dimensional superlattices on a large scale is required for their implementation into nano- or microelectronic devices1,2. This is achieved, generally after a size-selection process3,4, through spontaneous self-organization on a surface5,6,7,8,9,10,11, layer-by-layer deposition12 or the three-layer technique of oversaturation3,14, but these techniques consider superlattices of limited size. An alternative method developed in our group involves the direct formation in solution of crystalline superlattices, for example of tin nanospheres, iron nanocubes or cobalt nanorods, but these are also of limited size15,16,17. Here, we report the first direct preparation in solution of multimillimetre-sized three-dimensional compact superlattices of nanoparticles. The 15-nm monodisperse FeCo particles adopt an unusual short-range atomic order that transforms into body-centred-cubic on annealing at 500 ∘C. The latter process produces an air-stable material with magnetic properties suitable for radiofrequency applications.

Broad-band poly-harmonic distortion (PHD) behavioral models from fast automated simulations and large-signal vectorial network measurements

Abstract: We present an optimal experiment design methodology and a superior and fully automated model generation procedure for identifying a class of broad-band multiharmonic behavioral models in the frequency domain. The approach reduces the number of nonlinear measurements needed, minimizes the time to generate the data from simulations, reduces the time to extract the model functions from data, and when used for simulation-based models, takes maximum advantage of specialized simulation algorithms. The models have been subject to extensive validation in applications to real microwave integrated circuits. The derived model is valid for both small and large amplitude drive signals, correctly predicts even and odd harmonics through cascaded chains of functional blocks, simulates accurately load-pull behavior away from 50 /spl Omega/, and predicts adjacent channel power ratio and constellation diagrams in remarkably close agreement to the circuit model from which the behavioral model was derived. The model and excitation design templates for generating them from simulations are implemented in Agilent Technologies' Advanced Design System.

A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers

Abstract: A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mm /spl times/ 6.3 mm. The memory uses unidirectional programming currents controlled by locally mirrored write drivers to apply a robust toggle write sequence. An isolated read architecture driven by a balanced three input current mirror sense amplifier supports 25-ns cycle time asynchronous operation.

Physical insights regarding design and performance of independent-gate FinFETs

Abstract: Important physical insights regarding the design and performance of independent-gate FinFETs, e.g., the MIGFET , are gained from measured data and predictions from our process/physics-based double-gate (DG) MOSFET model (UFDG) in Spice3. Inversion charge-centroid shifting, modulated by gate biases as well as by quantum-confinement and short-channel effects, underlies the sensitivity of the MIGFET (front-gate) threshold voltage to the back-gate bias. MIGFET design and operation-mode options are examined for optimizing circuit applications. Further, novel design of a single-device RF mixer and a double-balanced counterpart using MIGFETs is studied with UFDG/Spice3. Reasonably good MIGFET mixers, with regard to conversion gain and linearity with small-size/low-voltage/low-power requirements, can be achieved with optimal biases on the two gates and good design of the MIGFET structure.

Method for making a semiconductor device with strain enhancement

Abstract: A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

Compressed representations of tries

Abstract: Techniques for representing nodes of tries. Associated with the nodes are keys and rules. A node of a trie having a stride n>1 is represented by a trie having a stride of 1 and the stride 1 trie is represented by a bit string termed a structural enumeration. The structural enumeration has a bit for each node of the trie of stride 1. If the node has a key and rule associated with it, the bit is set; otherwise it is not. The representation of a node of stride n>1 includes the node's structural enumeration and an array of rule pointers. The array has an entry for each rule associated with the node and the entries have the same order in the array as the set bits for their keys in the structural enumeration. Nodes having large strides may be represented by subdividing them into subtries.

Device and technology evolution for Si-based RF integrated circuits

Abstract: The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

A direct-conversion receiver for DVB-H

Abstract: A fully integrated low-power ultrahigh-frequency (UHF) tuner integrated circuit (IC) design for the digital video broadcasting-handheld (DVB-H) market is presented. A direct-conversion receiver is chosen over classical digital video broadcasting-terrestrial (DVB-T) architectures. The tuner IC covers UHF bands IV/V. The solution is based on a radio frequency integrated circuit (RFIC) and external low-noise amplifier (LNA) to meet the noise figure (NF) specification of 5 dB, IIP3 of 4dBm, and Gain of 89 dB. The IC includes an LNA, dual quadrature mixers, multiple bandwidth baseband (BB) filtering, three 4X voltage-controlled oscillators (VCOs), integer phase-locked loop (PLL), and reference oscillator. The design is implemented in a SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) technology and the die area is 11.5 mm/sup 2/.

Multi-protocol radio frequency identification transponder tranceiver

Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

Characterizing and comparing prevailing simulation techniques

Abstract: Due to the simulation time of the reference input set, architects often use alternative simulation techniques. Although these alternatives reduce the simulation time, what has not been evaluated is their accuracy relative to the reference input set, and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize the reduced input set, truncated execution, and sampling simulation techniques while also examining their speed versus accuracy trade-off and configuration dependence. Finally, to illustrate the effect that a technique could have on the apparent speedup results, we quantify the speedups obtained with two processor enhancements. The results show that: 1) the accuracy of the truncated execution techniques was poor for all three characterization methods and for both enhancements, 2) the characteristics of the reduced input sets are not reference-like, and 3) SimPoint and SMARTS, the two sampling techniques, are extremely accurate and have the best speed versus accuracy trade-offs. Finally, this paper presents a decision tree which can help architects choose the most appropriate technique for their simulations.

Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM

Abstract: The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65 nm eDRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high-k dielectrics and capacitor electrodes. � 2005 Elsevier Ltd. All rights reserved.

Method for packaging a semiconductor device

Abstract: A method for packaging a semiconductor device includes forming through holes ( 12 ) in a base substrate ( 10 ) and depositing a conductive material ( 14 ) on a first side ( 16 ) of the base substrate ( 10 ) to form a conductive layer ( 18 ) such that the conductive material ( 14 ) fills the through holes ( 12 ). The conductive layer ( 18 ) is patterned and etched to form interconnect traces and pads ( 22 ). Conductive supports ( 24 ) are formed on the pads ( 22 ) such that the conductive supports ( 24 ) extend through respective ones of the through holes ( 12 ).

Multiple fin formation

Abstract: A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.

Spin-transfer based mram using angular-dependent selectivity

Abstract: A magnetic random access memory (“MRAM”) device can be selectively written using spin-transfer reflection mode techniques. Selectivity of a designated MRAM cell within an MRAM array is achieved by the dependence of the spin-transfer switching current on the relative angle between the magnetizations of the polarizer element and the free magnetic element in the MRAM cell. The polarizer element has a variable magnetization that can be altered in response to the application of a current, e.g., a digit line current. When the magnetization of the polarizer element is in the natural default orientation, the data in the MRAM cell is preserved. When the magnetization of the polarizer element is switched, the data in the MRAM cell can be written in response to the application of a relatively low write current.

Transistor fabrication using double etch/refill process

Abstract: A semiconductor fabrication process includes forming a gate electrode ( 120 ) overlying a gate dielectric ( 110 ) overlying a semiconductor substrate ( 102 ). First spacers ( 124 ) are formed on sidewalls of the gate electrode ( 120 ). First s/d trenches ( 130 ) are formed in the substrate ( 102 ) using the gate electrode ( 120 ) and first spacers ( 124 ) as a mask. The first s/d trenches ( 130 ) are filled with a first s/d structure ( 132 ). Second spacers ( 140 ) are formed on the gate electrode ( 120 ) sidewalls adjacent the first spacers ( 124 ). Second s/d trenches ( 150 ) are formed in the substrate ( 102 ) using the gate electrode ( 120 ) and the second spacers ( 140 ) as a mask. The second s/d trenches ( 150 ) are filled with a second s/d structure ( 152 ). Filling the first and second s/d trenches ( 130, 150 ) preferably includes growing the s/d structures using an epitaxial process. The s/d structures ( 132, 152 ) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

High mobility NMOSFET structure with high-/spl kappa/ dielectric

Abstract: High-/spl kappa/ NMOSFET structures designed for enhancement mode operation have been fabricated with mobilities exceeding 6000 cm/sup 2//Vs. The NMOSFET structures which have been grown by molecular beam epitaxy on 3-in semi-insulating GaAs substrate comprise a 10 nm strained InGaAs channel layer and a high-/spl kappa/ dielectric layer (/spl kappa//spl cong/20). Electron mobilities of >6000 and 3822 cm/sup 2//Vs have been measured for sheet carrier concentrations n/sub s/ of 2-3/spl times/10/sup 12/ and /spl cong/5.85/spl times/10/sup 12/ cm/sup -2/, respectively. Sheet resistivities as low as 280 /spl Omega//sq. have been obtained.

High resolution pulse width modulator

Abstract: A pulse width modulator ( 100 ) and method that facilitates high resolution pulse width modulation is provided. The pulse width modulator ( 100 ) creates a pulse width modulated signal having a duty cycle that is proportional to a controllable delay in the modulator. The pulse width modulator combines a first digitally controllable delay ( 102 ) with a delay adjustment ( 104 ) to provide the controllable delay. In one embodiment, a digital counter ( 202 ) is used to provide coarse delay, with the delay adjustment device ( 210 ) coupled to the digital counter ( 202 ) to provide the fine, high resolution, delay control. Together the digital counter ( 202 ) and delay adjustment device ( 210 ) provide high resolution pulse width modulation. In one particular implementation, the analog delay adjustment device ( 100 ) comprises a delay block ( 500 ) designed to provide delay adjustment that is selectively controllable by changing a capacitance in the device.

Method for sharing bandwidth using reduced duty cycle signals and media access control

Abstract: A method is provided for transmitting data A first device generates a first signal having a first duty cycle, comprising a first gated-on portion and a first gated-off portion in a time slot; and a second device generates a second signal having second duty cycle, comprising a second gated-on portion and a second gated-off portion in the same time slot The first gated-on portion is generated during a first segment of the time slot and the first gated-off portion is generated during a second segment of the time slot, while the second gated-on portion is generated during the second segment and the second gated-off portion is generated during the first segment Media access control (MAC) can be used to further define positions within time slots and provide error correction, power control, and the like A preamble can be transmitted at an increased power level to facilitate acquisition

Power control feedback loop for adjusting a magnitude of an output signal

Abstract: A circuit for adjusting a magnitude of a transmit signal includes a transmitter (105), providing a transmit signal (107). It also includes a transmitter amplifier (109), receiving the transmit signal (107) and a power control adjustment signal (121), and responsive thereto, providing an amplified transmit signal (111). The circuit also includes a detector (123), for detecting an amplitude of the amplified transmit signal (111). Also included is an error component (137) for determining the difference between the amplitude and a reference level (129). Further provided is a digital signal generator (155), receiving the difference (145), and responsive thereto, generating (157) a reference signal (125) and the power control adjustment signal (117, 121), where the reference level (129) is responsive to the reference signal (125).

Metal gate transistor for cmos process and method for making

Abstract: A method for forming a semiconductor device (100) includes a semiconductor substrate having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and forming a capping layer (116) over the oxidation resistant barrier layer. In one embodiment, the conductive metal oxide is IrO2, MoO2, and RuO2, and the oxidation resistant barrier layer includes TiN.

Characterization of nickel Germanide thin films for use as contacts to p-channel Germanium MOSFETs

Abstract: We have measured the physical properties and resistivity of nickel germanide thin films formed by the rapid thermal annealing of nickel metal on p-type germanium substrates. Rutherford back scattering and high-resolution electron diffraction confirm that the stoichiometry of the resulting nickel germanide film corresponds to NiGe and has an orthorhombic unit cell with dimensions comparable to that of bulk samples. Transmission electron microscopy shows a poly-crystalline film structure with grain size > 0.1 /spl mu/m. The resistivity values for films annealed in the range 350/spl deg/C-500/spl deg/C are comparable to those of metal silicides. Measurements of the specific contact resistance suggest that values approaching 2 /spl times/ 10/sup -7/ /spl Omega/.cm/sup 2/ can be realized using NiGe formed on heavily doped p-type germanium.

Z-axis accelerometer with at least two gap sizes and travel stops disposed outside an active capacitor area

Abstract: An accelerometer includes a pair of conductive plates fixedly mounted on a substrate surface, a structure coupled to the substrate surface and suspended above the conductive plates, and at least one protective shield mounted on the substrate surface. The structure includes two regions of differing total moments disposed above a respective conductive plate and separated by a flexure axis about which the structure rotates during an acceleration normal to the substrate, each region having a substantially planar outer surface and an inner surface having a first corrugation formed thereon. For each of the two regions, an inner gap exists between the first corrugation and an opposing conductive plate, and an outer gap exists between the substantially planar outer surface and the opposing conductive plate, the outer gap being larger than the inner gap. The at least one protective shield is placed apart from either of the conductive plates.

Complex band structure and the band alignment problem at the Si-high-k dielectric interface

Abstract: We investigate the use of the complex band structure of high-$k$ gate dielectrics to estimate their charge neutrality levels, and compute band offsets to Si. A comparison is made with the available results obtained with direct electronic structure methods and experiment. It appears that charge neutrality levels thus obtained indeed provide a consistent picture for simple interfaces. However, the uncertainty in the conduction band position inherent in the local density approximation may render the theory inadequate for engineering support. Despite this limitation, linear rescaling of the charge neutrality levels based on the experimental band gaps for six oxides (${\mathrm{SiO}}_{2}$, ${\mathrm{Al}}_{2}{\mathrm{O}}_{3}$, $c\text{\ensuremath{-}}{\mathrm{HfO}}_{2}$, $m\text{\ensuremath{-}}{\mathrm{HfO}}_{2}$, ${\mathrm{La}}_{2}{\mathrm{O}}_{3}$, and ${\mathrm{SrTiO}}_{3}$) has shown excellent agreement with experimental data.

Media-independent handover (MIH) method featuring a simplified beacon

Abstract: A method for implementing a Media Independent Handover (MIH) service between one or more of a heterogeneous and a non-heterogeneous network (10, 90) comprises providing an MIH beacon (192) from one or more of a network (Net) (182) or a mobile node (MN) (186, 188, 190); acknowledging a receipt of the MIH beacon by another of the network (Net) or the mobile node; and facilitating handover (HO) services in response to an acknowledged receipt, and further in response to an MIH beacon message subsequently provided from one or more of the network (Net) or the mobile node. In one embodiment, the MIH beacon comprises at least an MIH-Capability (MIHC) flag, the MIHC flag having one of a first state or a second state.

Method and system for a single chip integrated Bluetooth and FM transceiver and baseband processor

Abstract: A method and system for a single chip integrated Bluetooth and FM transceiver and baseband processor are provided. The single chip may comprise a Bluetooth radio, an FM radio, a processor system, and a peripheral transport unit (PTU). FM data may be received and/or transmitted via the FM radio and Bluetooth data may be received and/or transmitted via the Bluetooth radio. The FM radio may receive radio data system (RDS) data. The PTU may support digital and analog interfaces. A processor in the processor system may time-multiplex processing of FM data and processing of Bluetooth data. The single chip may operate in an FM-only, a Bluetooth-only, and an FM-Bluetooth mode. The single chip may reduce power consumption by disabling portions of the Bluetooth radio during FM-only mode and/or disabling analog circuitry when performing digital processing. Communication between Bluetooth and FM channels may be enabled via the single chip.

Multi-protocol radio frequency identification reader tranceiver

Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.