Showing papers by "Freescale Semiconductor published in 2006"

Dynamic Maximum Power Point Tracking of Photovoltaic Arrays Using Ripple Correlation Control

Abstract: A dynamically rapid method used for tracking the maximum power point of photovoltaic arrays, known as ripple correlation control, is presented and verified against experiment The technique takes advantage of the signal ripple, which is automatically present in power converters The ripple is interpreted as a perturbation from which a gradient ascent optimization can be realized The technique converges asymptotically at maximum speed to the maximum power point without the benefit of any array parameters or measurements The technique has simple circuit implementations

Exact and approximate maximum likelihood localization algorithms

Abstract: Sensors at separate locations measuring either the time difference of arrival (TDOA) or time of arrival (TOA) of the signal from an emitter can determine its position as the intersection of hyperbolae for TDOA and of circles for TOA. Because of measurement noise, the nonlinear localization equations become inconsistent; and the hyperbolae or circles no longer intersect at a single point. It is now necessary to find an emitter position estimate that minimizes its deviations from the true position. Methods that first linearize the equations and then perform gradient searches for the minimum suffer from initial condition sensitivity and convergence difficulty. Starting from the maximum likelihood (ML) function, this paper derives a closed-form approximate solution to the ML equations. When there are three sensors on a straight line, it also gives an exact ML estimate. Simulation experiments have demonstrated that these algorithms are near optimal, attaining the theoretical lower bound for different geometries, and are superior to two other closed form linear estimators.

Optical critical points of thin-film Ge 1-y Sn y alloys: A comparative Ge 1-y Sn y /Ge 1-x Si x study

Abstract: The ${E}_{0}$, ${E}_{0}+{\ensuremath{\Delta}}_{0}$, ${E}_{1}$, ${E}_{1}+{\ensuremath{\Delta}}_{1}$, ${E}_{0}^{\ensuremath{'}}$, and ${E}_{2}$ optical transitions have been measured in ${\mathrm{Ge}}_{1\ensuremath{-}y}{\mathrm{Sn}}_{y}$ alloys $(yl0.2)$ using spectroscopic ellipsometry and photoreflectance. The results indicate a strong nonlinearity (bowing) in the compositional dependence of these quantities. Such behavior is not predicted by electronic structure calculations within the virtual crystal approximation. The bowing parameters for ${\mathrm{Ge}}_{1\ensuremath{-}y}{\mathrm{Sn}}_{y}$ alloys show an intriguing correlation with the corresponding bowing parameters in the ${\mathrm{Ge}}_{1\ensuremath{-}x}{\mathrm{Si}}_{x}$ system, suggesting a scaling behavior for the electronic properties that is the analog of the scaling behavior found earlier for the vibrational properties. A direct consequence of this scaling behavior is a significant reduction (relative to prior theoretical estimates within the virtual crystal approximation) of the concentration ${y}_{c}$ for a crossover from an indirect- to a direct-gap system.

Analysis of Software Aging in a Web Server

Abstract: Several recent studies have reported & examined the phenomenon that long-running software systems show an increasing failure rate and/or a progressive degradation of their performance. Causes of this phenomenon, which has been referred to as "software aging", are the accumulation of internal error conditions, and the depletion of operating system resources. A proactive technique called "software rejuvenation" has been proposed as a way to counteract software aging. It involves occasionally terminating the software application, cleaning its internal state and/or its environment, and then restarting it. Due to the costs incurred by software rejuvenation, an important question is when to schedule this action. While periodic rejuvenation at constant time intervals is straightforward to implement, it may not yield the best results. The rate at which software ages is usually not constant, but it depends on the time-varying system workload. Software rejuvenation should therefore be planned & initiated in the face of the actual system behavior. This requires the measurement, analysis, and prediction of system resource usage. In this paper, we study the development of resource usage in a web server while subjecting it to an artificial workload. We first collect data on several system resource usage & activity parameters. Non-parametric statistical methods are then applied toward detecting & estimating trends in the data sets. Finally, we fit time series models to the data collected. Unlike the models used previously in the research on software aging, these time series models allow for seasonal patterns, and we show how the exploitation of the seasonal variation can help in adequately predicting the future resource usage. Based on the models employed here, proactive management techniques like software rejuvenation triggered by actual measurements can be built

Piezoelectric micro-power generation interface circuits

Abstract: New power conversion circuits to interface to a piezoelectric micro-power generator have been fabricated and tested. Circuit designs and measurement results are presented for a half-wave synchronous rectifier with voltage doubler, a full-wave synchronous rectifier and a passive full-wave rectifier circuit connected to the piezoelectric micro-power generator. The measured power efficiency of the synchronous rectifier and voltage doubler circuit fabricated in a 0.35-/spl mu/m CMOS process is 88% and the output power exceeds 2.5 /spl mu/W with a 100-k/spl Omega/, 100-nF load. The two full-wave rectifiers (passive and synchronous) were fabricated in a 0.25-/spl mu/m CMOS process. The measured peak power efficiency for the passive full-wave rectifier circuit is 66% with a 220-k/spl Omega/ load and supplies a peak output power of 16 /spl mu/W with a 68-k/spl Omega/ load. Although the active full-wave synchronous rectifier requires quiescent current for operation, it has a higher peak efficiency of 86% with an 82-k/spl Omega/ load, and also exhibits a higher peak power of 22 /spl mu/W with a 68-k/spl Omega/ load which is 37% higher than the passive full-wave rectifier.

Charge storage structure formation in transistor with vertical channel region

Abstract: A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

A Statistical Traffic Model for On-Chip Interconnection Networks

Abstract: Network traffic modeling is a critical first step towards understanding and unraveling network power/performancerelated issues. Extensive prior research in the area of classic networks such as the Internet, Ethernet, and wireless LANs transporting TCP/IP, HTTP, and FTP traffic among others, has demonstrated how traffic models and model-based synthetic traffic generators can facilitate understanding of traffic characteristics and drive early-stage simulation to explore a large network design space. Though on-chip networks (a.k.a networks-on-chip (NoCs)) are becoming the de-facto scalable communication fabric in many-core systems-on-a-chip (SoCs) and chip multiprocessors (CMPs), no on-chip network traffic model that captures both spatial and temporal variations of traffic has been demonstrated yet. As available on-chip resources increase with technology scaling, enabling a myriad of new network architectures, NoCs need to be designed from the application’s perspective. In this paper we propose such an empirically-derived network on-chip traffic model for homogeneous NoCs. Our comprehensive model is based on three statistical parameters described with a 3-tuple, and captures the spatio-temporal characteristics of NoC traffic accurately with less than 5% error when compared to actual NoC application traces gathered from fullsystem simulations of three different chip platforms. We illustrate two potential uses of our traffic model: how it allows us to characterize and gain insights on NoC traffic patterns, and how it can be used to generate synthetic traffic traces that can drive NoC design-space exploration.

Etch method in the manufacture of an integrated circuit

Abstract: The present invention provides a method for etching a substrate in the manufacture of a semiconductor device, the method comprising contacting a surface of the substrate with ions extracted from a plasma formed from a gas comprising one or more of an oxygen-containing species, a nitrogen-containing species and an inert gas, and separately contacting the surface of the substrate with a plasma formed from a gas comprising a fluorine-containing species.

Implications of Proximity Effects for Analog Design

Abstract: This paper addresses two significant proximity effects, well proximity and STI stress, as they relate to analog circuit design. Device performance is impacted by layout features located near, but not part of the device. This adds new complexities to analog design. In either case, bias points can shift by 20-30%, causing potentially catastrophic failures in circuits. We show, for the first time, that a MOSFET placed close to a well-edge creates a graded channel.

A Predictive Performance Model for Superscalar Processors

Abstract: Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed simulation and several constraints that a processor design must satisfy. In this paper, we propose the use of empirical non-linear modeling techniques to assist processor architects in making design decisions and resolving complex trade-offs. We propose a procedure for building accurate non-linear models that consists of the following steps: (i) selection of a small set of representative design points spread across processor design space using latin hypercube sampling, (ii) obtaining performance measures at the selected design points using detailed simulation, (iii) building non-linear models for performance using the function approximation capabilities of radial basis function networks, and (iv) validating the models using an independently and randomly generated set of design points. We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a microarchitectural design space that consists of 9 key parameters. Our results show that the models, built using a relatively small number of simulations, achieve high prediction accuracy (only 2.8% error in CPI estimates on average) across a large processor design space. Our models can potentially replace detailed simulation for common tasks such as the analysis of key microarchitectural trends or searches for optimal processor design points.

Flexray - A communication network for automotive control systems

Abstract: The FlexRay protocol is reaching maturity quickly with a stable specification available for almost a year and a fully established conformance test in operation. This paper briefly reviews the main design goals of the FlexRay protocol, provides an overview of the evolution of the most relevant automotive networking protocols with some emphasis on safety-relevant features and finally discusses the most prominent applications.

Memory and method for sensing data in a memory using complementary sensing scheme

Abstract: In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

An introduction to IEEE STD 802.15.4

Abstract: The concept of simple sensor nets, devices the size of ping-pong balls, sprinkled liberally on the ground, has been around for a long time. Some of the big challenges have always been cost and complexity, as well as power consumption. While there have been a plurality of proprietary wireless systems developed over the past decade or so for application to this problem, these systems have suffered from an inability to scale well in cost and network complexity. In 2003, the IEEE 802.15.4 standard was ratified, and almost immediately silicon manufacturers began producing compliant single-chip radios. Now, the next generation of transceiver is on the horizon, complete with microcontroller and FLASH memory, as well as the potential for various environmental sensors to be built right into the silicon itself. IEEE STD 802.15.4 specifies the RF, PHY and MAC layers, and there are a variety of custom and industry-standards based networking protocols that can sit atop this IEEE stack. These networking protocols allow the rapid creation of mesh networks that are also self-healing. With energy-saving features designed into the basic IEEE standard, and other possibilities applied by the applications developer, IEEE 802.15.4 radios have the potential to be the cost-effective communications backbone for simple sensory mesh networks that can effectively harvest data with relatively low latency, high accuracy, and the ability to survive for a very long time on small primary batteries or energy-scavenging mechanisms like solar, vibrational, or thermal power. This paper will look closely at the IEEE standard and the features that are natively part of the standard. Some of the various networking protocols that are proposed for or being used on top of this standard will be discussed, including ZigBee networking and IPV6. Practical sensor devices employing the technology will be analyzed and power consumption investigated. In addition, the ongoing updates to the standard taking place now within the IEEE will be discussed in light of their potential to make products developed to this standard even more useful to the sensor community.

Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations

Abstract: Simulators have become an integral part of the computer architecture research and design process. Since they have the advantages of cost, time, and flexibility, architects use them to guide design space exploration and to quantify the efficacy of an enhancement. However, long simulation times and poor accuracy limit their effectiveness. To reduce the simulation time, architects have proposed several techniques that increase the simulation speed or throughput. To increase the accuracy, architects try to minimize the amount of error in their simulators and have proposed adding statistical rigor to their simulation methodology. Since a wide range of approaches exist and since many of them overlap, this paper describes, classifies, and compares them to aid the computer architect in selecting the most appropriate one.

Validation of MOSFET model Source–Drain Symmetry

Abstract: This paper presents dc and ac tests that verify whether a MOSFET model is symmetric with respect to a source-drain reversal. The tests are valid in the presence of and also verify the symmetry of gate and bulk currents, and evaluate the symmetry of all components of MOSFET charge models

A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC–DC Converters

Abstract: Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenges power supply designers. A novel interleaved discharging (ID) approach is presented to reduce the output ripple in step-down switched-capacitor (SC) dc-dc converters. Simulation and experimental results of a four-stage SC dc-dc converter show that the ID approach can reduce the output ripple by a factor of three. The proposed approach also improves the converter efficiency by 7%. The ID method provides flexibility in the design optimization of step-down SC dc-dc converters

Error correction device and methods thereof

Abstract: A device for error correction and methods thereof are disclosed. The method includes retrieving raw data from a memory device (104, 106) during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device (110) that interfaces with a variety of memory devices (104, 106). During a second operational phase, the raw data is outputted from the bus interface device to the bus master (102). In addition, error correction data is calculated (108), and error correction is performed on the raw data during the second operational phase (112). By retrieving the raw data before performing error correction, and by outputting the raw data and correcting the raw data during the same operational phase, data may be retrieved from the memory (104, 106) more rapidly.

Status and Outlook of MRAM Memory Technology (Invited)

Abstract: This paper provide an overview of the recent progress and the nature outlook of MRAM technology. Details of the operation, performance and reliability of Freescale's commercial 4Mbit MRAM device will be presented. Operation and reliability results demonstrating the extension of toggle MRAM to meet industrial and automotive requirements are presented, and new research results on higher-performance materials and advanced scaling approaches are discussed

MgO-based tunnel junction material for high-speed toggle magnetic random access memory

Abstract: We report the first demonstration of a magnetoresistive random access memory (MRAM) circuit incorporating MgO-based magnetic tunnel junction (MTJ) material for higher performance. We compare our results to those of AlOx-based devices, and we discuss the MTJ process optimization and material changes that made the demonstration possible.We present data on key MTJ material attributes for different oxidation processes and free-layer alloys, including resistance distributions, bias dependence, free-layer magnetic properties, interlayer coupling, breakdown voltage, and thermal endurance. A tunneling magnetoresistance (TMR) greater than 230% was achieved with CoFeB free layers and greater than 85% with NiFe free layers. Although the TMR with NiFe is at the low end of our MgO comparison, even this MTJ material enables faster access times, since its TMR is almost double that of a similar structure with an AlOx barrier. Bit-to-bit resistance distributions are somewhat wider for MgO barriers, with sigma about 1.5% compared to about 0.9% for AlOx. The read access time of our 4 Mb toggle MRAM circuit was reduced from 21 ns with AlOx to a circuit-limited 17 ns with MgO.

Spin-transfer based MRAM with reduced critical current density

Abstract: A magnetic random access memory device include a spin torque MRAM cell ( 100 ) having a reduced switching current (I c ) wherein standard materials may be used for a free layer ( 108 ). A fixed magnetic element ( 112 ) polarizes electrons passing therethrough, and the free magnetic element ( 108 ) having a first plane anisotropy comprises a first magnetization ( 130 ) whose direction is varied by the spin torque of the polarized electrons. An insulator ( 110 ) is positioned between the fixed magnetic element ( 112 ) and the free magnetic element ( 108 ), and a keeper layer ( 104 ) positioned contiguous to the free magnetic element ( 108 ) and having a second plane anisotropy orthogonal to the first plane anisotropy, reduces the first plane anisotropy and hence reduces the spin torque switching current (I c ). The keeper layer ( 104 ) may include alternating synthetic antiferromagnetic layers ( 132, 134 ) of magnetization approximately equal in magnitude and opposite in direction.

Superimposed training for OFDM: a peak-to-average power ratio analysis

Abstract: Orthogonal frequency division multiplexing (OFDM) transmission with superimposed training is considered in this paper. One major disadvantage of OFDM is the significant amplitude fluctuations, i.e., high peak-to-average power ratios (PARs). High PARs require large backoff of the average operating power of a radio-frequency (RF) power amplifier (PA) in order to linearly amplify the signal, thus reducing the dc to RF power conversion efficiency. The PAR of the OFDM signal is examined with superimposed training, and its complementary cumulative distribution function (CCDF) is derived. Achievable lower and upper bounds on the CCDF are also determined. In addition, the PAR change is linked to the effective signal-to-noise ratio (SNR) and thus the bit-error-rate (BER) performance under the fixed dc power constraint. Simulation results are presented to illustrate the proposed PAR and power analysis for OFDM with superimposed training.

Effect of contact metallization on electromigration reliability of Pb-free solder joints

Abstract: The effect of underbump metallization (UBM) on electromigration (EM) lifetime and failure mechanism has been investigated for Pb-free solder bumps of 97Sn3Ag composition in the temperature range of 110–155°C. The EM lifetime of the SnAg Pb-free solders with either Cu or Ni UBM was found to be better than the eutectic SnPb (63Sn37Pb) solders but worse than high-Pb (95Pb5Sn) solders. In the test temperature range, the EM lifetimes were found to be comparable for Cu and Ni UBMs but with different activation energies: 0.64–0.72eV for Cu UBM and 1.03–1.11eV for Ni UBM. EM failure was observed only in solder bumps with electron current flow from UBM to the substrate. Failure analysis revealed that EM damage was initiated by the formation of intermetallic compounds (IMC) at the UBM∕solder interface which was found to be significantly enhanced by mass transport driven by the electron current. Under EM, the continued growth of IMC with the dissolution of the UBM and the accumulation of Kirkendall voids resulted in...

A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver

Abstract: This paper describes the design and performance of the first tri-band (2100, 1900, 800/850 MHz) single-chip 3G cellular transceiver IC for worldwide use. The transceiver has been designed to meet all narrowband blocker, newly proposed Adjacent Channel II, and Category 10 HSDPA (High Speed Downlink Packet Access) requirements. The design is part of a reconfigurable reference platform for multi-band, multi-mode (GSM/EDGE + WCDMA) radios. The zero-IF receiver is comprised of a novel multi-band quadrature mixer, seventh-order baseband filtering, and a novel DC offset correction scheme, which exhibits no settling time or peak switching transients after gain steps. The receiver lineup is designed to optimize HSDPA throughput and minimize sensitivity to analog baseband filter bandwidth variations. The direct-launch transmitter is made up of a third-order baseband filter, an I/Q modulator with variable gain, an integrated transformer, an RF variable gain amplifier, and a power amplifier driver. At +9.5-dBm output power, the transmitter achieves an error vector magnitude (EVM) of 4%. Fractional-N synthesizers achieve fast lock times of 50 /spl mu/s (150 /spl mu/s) within 20 ppm (0.1 ppm). Automatically calibrated, integrated VCOs achieve a 1.6-GHz tuning range to facilitate coverage over all six 3GPP frequency bands. The IC draws 34 mA in receive (18-mA receiver plus 16-mA fractional-N PLL/VCO) and 50 to 62 mA in transmit (-76 dBm to +9.5 dBm), including PLL/VCO, using a 2.775-V supply voltage. The RF transceiver is integrated with the baseband signal processing and associated passives in a 165-pad package, resulting in the first tri-band 3G radio transceiver with a digital interface which requires no external components.

A method of making an inverted-t channel transistor

Abstract: A method for creating an inverse T field effect transistor (10) is provided. The method includes creating a horizontal active region (14) and a vertical active region (16) on a substrate (12). The method further comprises forming a sidewall spacer (22) on a first side of the vertical active region and a second side of the vertical active region (16). The method further includes removing a portion of the horizontal active region (14), which is not covered by the sidewall spacer (22). The method further includes removing the sidewall spacer (22). The method further includes forming a gate dielectric (26) over at least a first part of the horizontal active region (14) and at least a first part of the vertical active region (16). The method further includes forming a gate electrode (28) over the gate dielectric (26). The method further includes forming a source region (30) and a drain region (32) over at least a second part of the horizontal active region and at least a second part of the vertical active region (16).

Methods and apparatus for simulating distributed effects

Abstract: In general, various embodiments of the present invention relate to systems and methods for simulating distributed effects by providing a meshing pattern (200) (e.g., a two-dimensional meshing pattern that is part of a recognition layer), applying that meshing pattern to the physical layout (100), and partitioning the physical layout into a three-dimensional netlist (300) of components derived from the unit cells defined by the meshing pattern (200), thereby modeling the parasitics within the design.

Enhancement-Mode GaAs n-Channel MOSFET

Abstract: This letter introduces the first enhancement-mode GaAs n-channel MOSFETs with a high channel mobility and an unpinned Fermi level at the oxide/GaAs interface. The NMOSFETs feature an In0.3Ga0.7 As channel layer, a channel mobility of up to 6207 cm2/Vmiddots, and a dielectric stack thickness of 13.1-18.7 nm. Enhancement-mode NMOSFETs with a gate length of 1 mum, a source/drain spacing of 3 mum, and a threshold voltage of 0.05 V show a saturation current, transconductance, on-resistance, and subthreshold swing of 243 mA/mm, 81 mS/mm, 8.0 Omegamiddotmm, and 162 mV/dec, respectively

Stackable molded packages and methods of making the same

Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Semiconductor device with a protected active die region and method therefor

Abstract: A semiconductor device includes a semiconductor die having a plurality of contact pad sites, a plurality of contact pads, an encapsulant barrier, and an encapsulant. A plurality of contact pads is in electrical contact with a predetermined corresponding different one of the contact pad sites. An encapsulant barrier is positioned at an outer perimeter of the semiconductor die. The encapsulant barrier has a height that is as high as or greater than a highest of the plurality of contact pads. The encapsulant barrier is in physical contact with a same surface of the semiconductor die as the contact pad sites. An encapsulant surrounds the semiconductor die and one side of the encapsulant barrier. The encapsulant is blocked from making physical contact with any of the plurality of contact pads by the encapsulant barrier when the device is encapsulated while being supported by a temporary base support layer.

Feedback reduction for MIMO precoded system by exploiting channel correlation

Abstract: In a closed-loop wireless communication system, a codebook-based precoding feedback compression mechanism is provided to remove redundancy from the precoding feedback that is caused by channel correlation in time and frequency Redundancy due to temporal correlation of the transmission channel is removed by sending precoding feedback only if there is a change in the precoder state for the channel to the receiver Redundancy due to frequency correlation is removed by run length encoding the precoding feedback, thereby compressing the precoding feedback prior in the frequency domain By compressing the precoding feedback, the average rate of precoder feedback is reduced

Estimation of fixed charge densities in hafnium-silicate gate dielectrics

Abstract: In this paper, an effective technique and methodology for the estimation of fixed charge components in high-k stacks was demonstrated by varying both the SiO2 and high-k dielectric thicknesses. The SiO2 thickness was scaled on a single wafer by uniformly changing the etch time of a thermally grown SiO2 layer across the wafer. This minimized wafer-to-wafer variations and enables acquisition of statistically significant datasets. Layers with different thickness of both the nitrided and non-nitrided hafnium-silicate layers were then grown on these wafers to estimate all the interfacial and bulk charge components. The reproducibility and validity of this technique were demonstrated, and this method was used to compare the fixed charge levels in Hf-silicates (HfSiO) and nitrided-Hf-silicate (HfSiON) layers