Showing papers by "Freescale Semiconductor published in 2013"

A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation

Abstract: Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is ${-}$ 105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply.

Flash memory with BIAS voltage for word line/row driver

Abstract: A memory device includes a word line driver circuit 116, a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit, and a write bias generator 106 including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit. The write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit.

A Nonlinear Controller Based on a Discrete Energy Function for an AC/DC Boost PFC Converter

Abstract: AC/DC converter systems generally have two stages: an input power factor correction (PFC) boost ac/dc stage that converts input ac voltage to an intermediate dc voltage while reducing the input current harmonics injected to the grid, followed by a dc/dc converter that steps up or down the intermediate dc-bus voltage as required by the output load and provides high-frequency galvanic isolation. Since a low-frequency ripple (second harmonic of the input ac line frequency) exists in the output voltage of the PFC ac/dc boost converter due to the power ripple, the voltage loop in the conventional control system must have a very low bandwidth in order to avoid distortions in the input current waveform. This results in the conventional PFC controller having a slow dynamic response against load variations with adverse overshoots and undershoots. This paper presents a new control approach that is based on a novel discrete energy function minimization control law that allows the front-end ac/dc boost PFC converter to operate with faster dynamic response than the conventional controllers and simultaneously maintain near unity input power factor. Experimental results from a 3-kW ac/dc converter built for charging traction battery of a pure electric vehicle are presented in this paper to validate the proposed control method and its superiority over conventional controllers.

Dynamic Healing Of Non-Volatile Memory Cells

Abstract: Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

Cyclic spectral analysis of power line noise in the 3–200 kHz band

Abstract: Narrowband OFDM Power Line Communication (NB-OFDM PLC) systems are a key component of current and future smart grids. NB-OFDM PLC systems enable next-generation smart metering, distributed control, and monitoring applications over existing power delivery infrastructure. It has been shown that the performance of these systems is severely limited by impulsive, non-Gaussian additive noise. A substantial component of this noise has time-periodic statistics (i.e. it is cyclostationary) synchronous to the AC mains cycle. In this work, we analyze the cyclic structure of power line noise observed in a G3 PLC system operating in the CENELEC 3-148.5 kHz band. Our contributions include: (i) the characterization of noise measurements in several urban usage environments, (ii) the development of a cyclic bit loading method for G3, and (iii) the quantification of its throughput gains over measured noise. Through this analysis, we confirm strong cyclostationarity in power lines and identify several sources of the cyclic noise.

Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology

Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.

Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates ( 118, 128 ) on a first substrate area ( 111 ) which are encapsulated in one or more planar dielectric layers ( 130 ) prior to forming in-laid high-k metal select gates and CMOS transistor gates ( 136, 138 ) in first and second substrate areas ( 111, 113 ) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Non-volatile memory (nvm) and logic integration

Abstract: A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic

Abstract: A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

Logic transistor and non-volatile memory cell integration

Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.

Mems sensor device with multi-stimulus sensing and method of fabrication

Abstract: A device (20) includes sensors (30, 32, 34) that sense different physical stimuli. Fabrication (90) entails forming (92) a device structure (22) to include the sensors and coupling (150) a cap structure (24) with the device structure so that the sensors are interposed between the cap structure and a substrate layer (28) of the device structure. Fabrication (90) further entails forming ports (38, 40) in the substrate layer (28) such that one port (38) exposes a sense element (44) of the sensor (30) to an external environment (72), and another port (40) temporarily exposes the sensor (34) to the external environment. A seal structure (26) is attached to the substrate layer (28) such that one port (40) is hermetically sealed by the seal structure and an external port (46) of the seal structure is aligned with the port (38).

MISHFET and Schottky device integration

Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

Semiconductor device with self-biased isolation

Abstract: A method of fabricating a reduced surface field (RESURF) transistor includes forming a first well in a substrate, the first well having a first conductivity type, doping a RESURF region of the first well to have a second conductivity type, doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type, and forming a second well in the substrate, the second well having the second conductivity type. A plug region is formed in the substrate, the plug region extending to the RESURF region.

Improving electronic sensor reliability by robust outlier screening.

Abstract: Electronic sensors are widely used in different application areas, and in some of them, such as automotive or medical equipment, they must perform with an extremely low defect rate. Increasing reliability is paramount. Outlier detection algorithms are a key component in screening latent defects and decreasing the number of customer quality incidents (CQIs). This paper focuses on new spatial algorithms (Good Die in a Bad Cluster with Statistical Bins (GDBC SB) and Bad Bin in a Bad Cluster (BBBC)) and an advanced outlier screening method, called Robust Dynamic Part Averaging Testing (RDPAT), as well as two practical improvements, which significantly enhance existing algorithms. Those methods have been used in production in Freescale® Semiconductor probe factories around the world for several years. Moreover, a study was conducted with production data of 289,080 dice with 26 CQIs to determine and compare the efficiency and effectiveness of all these algorithms in identifying CQIs.

Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects

Abstract: The population of small-delay defects (SDDs) in integrated circuits increases significantly as technology scales to 65 nm and below. Therefore, testing for SDDs is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. Commercial timing-aware automatic test pattern generation (ATPG) tools have been developed for SDD detection. However, they only use static timing analysis reports in the form of standard delay format for path-length calculation and neglect important underlying causes, such as process variations, crosstalk, and power-supply noise, which can also induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more LPs, detects more SDDs with a much smaller pattern count, and needs less CPU runtime compared with a commercial timing-aware ATPG tool.

Microelectronic packages containing stacked microelectronic devices and methods for the fabrication thereof

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes encapsulating a device stack within a molded panel having a frontside and a backside. The device stack contains an upper semiconductor die and an interconnect buffer layer, which is formed over the upper semiconductor die and which is covered by the frontside of the molded panel. Material is removed from the frontside the molded panel to expose the interconnect buffer layer therethrough. One or more frontside redistribution layers are produced over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer. The molded panel is then singulated to yield a microelectronic package including a molded package body containing the device stack.

Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs

Abstract: Preface List of physical constants List of symbols 1. Introduction 2. Unique features of UTB MOSFETs 3. Planar fully depleted SOI MOSFETs 4. FinFETs Appendix: UFDG References Index.

Systems and method for gyroscope calibration

Abstract: A mechanism by which a MEMS gyroscope sensor can be calibrated using data gathered from other sensors in a system incorporating the MEMS gyroscope sensor is provided. Data gathered from an accelerometer and a magnetometer in fixed orientation relative to the gyroscope is used to calculate changes in orientation of a system. A constant acceleration vector measured by the accelerometer and a constant magnetic vector measured by the magnetometer are used as reference vectors in a solution to Wahba's problem to calculate a rotation matrix providing the system's orientation with respect to those two constant vectors. By comparing changes in orientation from one time to a next time, measured rates of angular change can be calculated. The measured rates of angular change can be used along with observed gyroscope rates of angular change as input to a linear regression algorithm, which can be used to compute gyroscope trim parameters.

Angular rate sensor having multiple axis sensing capability

Abstract: An angular rate sensor ( 20 ) includes a single drive mass ( 24 ) and distributed sense masses ( 36, 38, 40, 42 ) located within a central opening ( 30 ) of the drive mass ( 24 ). The drive mass ( 24 ) is enabled to rotate around the Z-axis ( 64 ) under electrostatic stimulus. The sense masses ( 36, 38, 40, 42 ) are coupled to the drive mass by spring elements ( 44, 46, 48, 50 ) such that oscillatory rotary motion ( 90 ) of the drive mass imparts a linear drive motion ( 92, 94 ) on the sense masses. The distributed sense masses form two pairs of sense masses, where one pair senses X- and Z-axis angular rate and the other pair senses Y- and Z-axis angular rate. The sense masses are coupled to one another via a centrally located coupler element ( 34 ) to ensure that the sense masses of each pair are moving in anti-phase.

Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells ( 105 - 109, 113 - 115 ) on a first flash cell substrate area ( 111 ) which are encapsulated in one or more planar dielectric layers ( 116 ) prior to forming an elevated substrate ( 117 ) on a second CMOS transistor area ( 112 ) on which high-k metal gate electrodes ( 119 - 120, 122 - 126, 132, 134 ) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Electronic circuits with variable attenuators and methods of their operation

Abstract: Variable attenuators (200, 400, 618, 620) and methods of their operation are provided. A variable attenuator (200, 400, 618, 620) includes first and second variable resistance circuits (210, 411, 250, 451) and multiple additional resistors (222, 223, 230, 231, 423, 424, 432, 433). The first variable resistance circuit (210, 411) has a plurality of current paths (212, 213, 214, 414, 415) coupled in parallel between input and output terminals (202, 405, 204, 406). A first current path (213, 415) includes two first resistors (222, 223, 423, 424) coupled in series between the input and output terminals, and a switch (230, 432), which has a channel coupled across one of the two first resistors. The multiple additional resistors include second and third resistors (230, 432, 231, 433). The second resistor (230, 432) is coupled between the input terminal and an intermediate node (206, 408). The third resistor (231, 433) is coupled between the output terminal and the intermediate node (206, 408). The second variable resistance circuit (250, 451) is coupled between the intermediate node and a voltage reference terminal (270, 470). The level of attenuation provided by the attenuator is controlled by a switch control circuit (300, 500) based on a digital input.

Multiple sense axis MEMS gyroscope having a single drive mode

Abstract: A gyroscope (20) includes a first drive mass (22) driven in a first drive motion (140) along a first axis (100), the first drive motion (140) generating a first sense motion (144) of a first sense mass (68) in response to rotation of the gyroscope (20). The gyroscope (20) further includes a second drive mass (24) driven in a second drive motion (142) along a second axis (102) that is transverse to the first axis (100). The second drive motion (142) generates a second sense motion (146) of a second sense mass (70) in response to rotation of the gyroscope (20). A drive spring system (36) interconnects the two drive masses (22, 24) to couple the first and second drive motions (140, 142) so that a single drive mode (98) can be implemented. The sense motion (144, 146) of each sense mass (68, 70) is along a third axis (118), where the third axis (118) is transverse to the other axes (100, 102). The sense motion (144, 146) is translational motion such the sense masses (68, 70) remain parallel to the surface (30) of the substrate (32).

Vehicle-borne radar systems with continuous-time, sigma delta analog-to-digital converters, and methods of their operation

Abstract: Embodiments of vehicle-borne radar systems (202) and methods of their operation are provided. The vehicle-borne radar system (202) includes a transmit path (210) and a first receive path (220). The transmit path is capable of producing (502) a signal for transmission over an air interface (e.g., a frequency modulated continuous wave (FMCW) signal). The receive path includes a continuous-time (CT) sigma delta analog-to-digital converter (ADC) (228), and the receive path is capable of receiving (504) a reflected version of the signal from the air interface, and converting the reflected version along the receive path into a sequence of digital samples using the CT sigma delta ADC. In an embodiment, the transmit path and the receive path are integrated onto a single integrated circuit.

Adaptive adjustment of power splitter

Abstract: A device includes a power splitter (501) configured to couple to an amplifier having a first path (517) and a second path (523). The device includes a controller (527) coupled to first and second variable attenuators (515, 521) and first and second adjustable phase shifters (513, 519). The controller is configured to monitor a phase shift and an output power of each of the first path and second path of the amplifier, and adjust at least one of the first and second variable attenuators and the first and second adjustable phase shifters based upon the phase shift and the output power of each of the first path and second path of the amplifier to modify an input signal to the first path or the second path of the amplifier.

Wireless power transmitters with wide input voltage range and methods of their operation

Abstract: The embodiments described herein provide a power transmitter for wireless charging of an electronic device and methods of its operation. The power transmitter uses an inverter configured to generate a square wave from a potentially wide ranging DC input voltage. The inverter is configured to generate the square wave with a duty cycle that results in a desired equivalent voltage output, effectively independent of the DC input voltage that is provided. Thus, by generating a square wave with a selectable duty cycle the inverter provides the ability to facilitate wireless power transfer with a wide range of DC input voltages. Furthermore, in some embodiments the power transmitter may provide improved power transfer efficiency using a quasi-resonant phase shift control strategy with adjustable dead time and a matching network that is dynamically selectable to more effectively couple with the transmitter coil combination being used to transmit power to the electronic device.

Simulation knowledge extraction and reuse in constrained random processor verification

Abstract: This work proposes a methodology of knowledge extraction from constrained-random simulation data. Feature-based analysis is employed to extract rules describing the unique properties of novel assembly programs hitting special conditions. The knowledge learned can be reused to guide constrained-random test generation towards uncovered corners. The experiments are conducted based on the verification environment of a commercial processor design, in parallel with the on-going verification efforts. The experimental results show that by leveraging the knowledge extracted from constrained-random simulation, we can improve the test templates to activate the assertions that otherwise are difficult to activate by extensive simulation.

Approach to the silicon limit: Advanced NLDMOS in 0.13 μm SOI technology for automotive and industrial applications up to 110V

Abstract: We report our development of a novel NLDMOS in SOI based smart power technology, integrated into Freescale's 0.13μm CMOS platform. The new NLDMOS not only achieves BVDSS up to 140V in both low side and high side operations, but more importantly, the Rdson*Area is able to shrink at least 35-40% below the current benchmark, which is the lowest reported for BVDSS ranging from 50V to 138V. For the first time, we demonstrated LDMOS devices which approach the Si limit. The devices also achieve very competitive performance in both SOA and the reliability tests under HCI stress as well as high temperature reverse bias (HTRB) stress.