Showing papers by "Freescale Semiconductor published in 2017"

Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging

Abstract: Shared Memory stands out as a sine qua non for parallel programming of many commercial and emerging multicore processors. It optimizes patterns of communication that benefit common programming styles. As parallel programming is now mainstream, those common programming styles are challenged with emerging applications that communicate often and involve large amount of data. Such applications include graph analytics and machine learning, and this paper focuses on these domains. We retain the shared memory model and introduce a set of lightweight in-hardware explicit messaging instructions in the instruction set architecture (ISA). A set of auxiliary communication models are proposed that utilize explicit messages to accelerate synchronization primitives, and efficiently move computation towards data. The results on a 256-core simulated multicore demonstrate that the proposed communication models improve performance and dynamic energy by an average of 4x and 42% respectively over traditional shared memory.

Common public radio interface, CPRI, lane controller and method of operating thereof

Abstract: The present application relates to a Common Public Radio Interface, CPRI, lane controller and a method of operating thereof. The CPRI lane controller comprises a transaction counter, a symbol counter and a comparator. The transaction counter is provided for maintaining a current aggregated transactions' size, Sizetrans, representative of an accumulated size of DMA transactions performed by a DMA controller in response to symbols transferred on a CPRI link from or to the CPRI lane controller. The symbol counter is provided for maintaining a current aggregated expected symbols' size, Sizeexp, representative of an accumulated size of a sequence of transferred symbols and a currently transferred symbol. The comparator is configured to issue a symbol awareness signal, SAS, in case the current aggregated transactions' size, Sizetrans, exceeds the current aggregated expected symbols' size, Sizeexp.

Slave device alert signal in inter-integrated circuit (i2c) bus system

Abstract: A system having master and slave devices and communicating over an I2C bus has SDA and a SCL lines that are normally high unless a device pulls the voltage of the line Low. Normal data signals on the SDA line are set during the low phase of the clock signals on the SCL line and transferred to a receiver during the high phase of the clock signals. A slave device provides an alert signal on the SDA line during the low phase of the clock signals to send an alert signal to the master device. The alert signal may be a pulse signaling the slave device wakeup or a pulse pattern identifying the alerting slave device.

High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFet

Abstract: A CMOS bandgap reference (BGR) circuit with low mismatch spread is proposed. A conventional BGR circuit uses a CMOS error amplifier and its input offset causes large spread in the bandgap output voltage. The proposed BGR circuit does not use a separate error amplifier. Instead, the bipolar transistor pair used to generate ΔVbe acts as input differential pair as well resulting in low mismatch spread. It can generate the typical 1.22V as well as any number of less than 1.22V bandgap outputs simultaneously without requiring a separate voltage divider circuit. As compared to other offset reduction techniques such as chopping which require a clock and extra area, the proposed BGR circuit is very simple to implement. The proposed BGR circuit has been designed in 16nm FinFet technology for a wide temperature range of -40°C to 125°C and supply voltage range of 1.8V ± 10%. The post-layout extracted simulation results and silicon characterization results are in close agreement. The silicon results show that the maximum peak to peak variation is 8mV or 1.3% for a bandgap output of 0.605V. The proposed BGR consumes 340µW power at 1.8V.

Communicaton unit receiver, integrated circuit and method for adc dynamic range selection

Abstract: A communication unit receiver comprising: a multi-section analogue to digital converter, ADC, configured to receive an analogue signal and convert at least a first portion of the analogue signal into a digital signal using a first ADC dynamic range. A modem, coupled to the multi-section ADC, is configured to: process the digital signal; determine a signal-to-noise ratio, SNR, for sub-carriers of the analogue signal; and output an ADC selection signal to the multi-section ADC that selects a subset of sections of the multi-section ADC, where the selection signal is based at least partly on the determined SNR. Only the subset of sections of the multi-section analogue to digital converter, ADC is configured to convert a second portion of the analogue signal into a digital signal using a second ADC dynamic range that is less than the first dynamic range.

Cache organization and method

Abstract: A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced.

Video encoder with adjustable intra-refresh rate

Abstract: An encoding system for converting video data to a media stream based on a given intra-refresh rate includes an encoder for encoding the video data to frames based on the given intra-refresh rate, a decoder for reconstructing the encoded frames, and an evaluation unit for scoring macro blocks (MBs) of a current frame being decoded. A score of an intra-MB is defined as a predetermined value, and a score of an inter-MB is generated based on the scores of MBs of previous frames. A controller determines an actual refresh period based on a qualified frame identified based on the scores of the MBs of at least the current frame, and adjusts the given intra-refresh rate based on the actual refresh period.

Magnetic field sensor with multiple sense layer magnetization orientations

Abstract: A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization. A permanent magnet layer spaced apart from the sense elements magnetically biases the sense magnetization into an out-of-plane direction that is non-perpendicular to the plane of the sensor. The sense magnetization of a portion of the sense elements is oriented in a first direction and the sense magnetization of a different portion of the sense elements is oriented in a second direction differing from the first direction to generate two unique bias field vectors of the sense layers which enables detection of the external magnetic field in a sensing direction that is perpendicular to the plane of the magnetic field sensor without inter-axis coupling of sensor response.

Data clustering employing mapping and merging

Abstract: A data-clustering method generates data clusters for a set of data points. A region of interest containing the data points and a center matrix for the region of interest are defined, where the center matrix includes an array of center points defining centers of overlapping circles. The data points are mapped to corresponding circles based on near center points. Pairs of overlapping circles are merged based on relative numbers of data points lying in overlap regions of the pairs of overlapping circles compared to total numbers of data points within the corresponding circles. Circles belonging to the one or more data clusters are identified based on merged pairs of overlapping circles, and data points belonging to the one or more data clusters are identified based on the corresponding circles. The method may be performed by a computer having a heterogeneous architecture with parallel processors.

Solid state microwave heating apparatus with stacked dielectric resonator antenna array, and methods of operation and manufacture

Abstract: An embodiment of a microwave heating apparatus includes a solid state microwave energy source, a first dielectric resonator antenna that includes a first exciter dielectric resonator and a first feed structure in proximity to the first exciter dielectric resonator, one or more additional dielectric resonators stacked above the top surface of the first exciter dielectric resonator to form a vertically-stacked dielectric resonator antenna array The first feed structure is electrically coupled to the microwave energy source to receive a first excitation signal, and the first exciter dielectric resonator is configured to produce a first electric field in response to the excitation signal provided to the first feed structure

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

Abstract: A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

Designing a Density Driven Integrated Circuit

Abstract: A design tool system includes a schematic design tool that computes a total number of devices in an analog circuit schematic based on information extracted from the analog circuit schematic. The schematic design tool selects an optimal row/column device configuration for the total number of devices and creates a temporary layout based upon the optimal row/column device configuration. The schematic design tool computes layout structure data based on the temporary layout and provides the layout structure data to a place and route tool within the design tool system that, in turn, generates a layout based on the layout structure data The design tool system then generates mask layer data based upon the layout that is configured to generate masks for construction of an integrated circuit corresponding to the analog circuit schematic.

Integrated circuit with low power scan system

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches for receiving a first input signal and the second latch signal, and generating a scan data output signal depending on a trig signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the trig signal.

Mems sensor device having integrated multiple stimulus sensing

Abstract: A sensor device comprises a device structure and a cap coupled with the device structure to produce a cavity in which components of the sensor device are located. The device structure includes a substrate and a movable element spaced apart from a surface of the substrate. A port extends through the substrate underlying the movable element. A sense element is spaced apart from the movable element and is displaced away from the port. The movable element and the sense element form an inertial sensor to sense a motion stimulus as movement of the movable element relative to the sense element. An additional sense element together with a diaphragm spans across the port. The movable element and the additional sense element form a pressure sensor for sensing a pressure stimulus from an external environment as movement of the additional sense element together with the diaphragm relative to the movable element.

Passive equalizer capable of use in high-speed data communication

Abstract: A passive equalizer is provided. The passive equalizer includes a first resistive element, a first inductive element, a second resistive element, and a first variable capacitor. The first resistive element is coupled between an input node and an output node. The first inductive element and the second resistive element are coupled in series between the output node and a first voltage supply node. The first variable capacitor is coupled between the input node and a first node located between the first inductive element and the second resistive element.

Operational Transconductance Amplifier-based Sinusoidal Oscillator with Grounded Capacitors

Abstract: A sinusoidal oscillator using two capacitors and three operational transconductance amplifiers (OTAs) is presented. Taking the aid of single-ended OTA, the current-mode sinusoidal oscillator circuit in parts a simple circuitry, that has been stated to be highly suitable for implementation of integrated circuit which in turn use grounded capacitors. The condition of oscillation (CO) and frequency of oscillation (FO) of the same circuit can be set orthogonally. The sinusoidal oscillator is mainly implemented in communication systems, instrumentation programs, measurement devices, and signal processing. The mathematical derivations thus obtained in the circuit can be verified with cadence using model parameters of 180 nm technology process. However, the results arrived have demonstrated excellent agreement with the theoretical values.

Pressure sensor device and method for testing the pressure sensor device

Abstract: A pressure sensor device and a method for testing the pressure sensor device is provided. The pressure sensor device includes a first pressure sensor cell having a first capacitance value, and a second pressure sensor cell having a second capacitance value, the second capacitance value being different from the first capacitance value. In one embodiment, the method includes determining a temperature coefficient offset to test for faults in the pressure sensor device. In another embodiment, the method includes determining a differential mode calculation and a common mode calculation. A fault exists if the differential and common mode calculations do not agree.

Receiver removal detection in wireless charging systems

Abstract: A wireless charging system has a transmitter and a receiver. The transmitter has (i) a TX coil that wirelessly transfers power to the receiver and (ii) TX circuitry that powers the TX coil and detects receiver removal by comparing TX input power and TX power loss. The TX circuitry can determine (1) TX input power as the product of sampled TX input current and voltage and (2) TX power loss using a mapping based on sampled TX coil current. When the receiver is present, the difference between TX input power and TX power loss has a first value and when the receiver is removed, the difference has a second, lesser value. The transmitter detects removal of the receiver by determining when the difference decreases below a specified threshold level. By frequently generating and analyzing the difference, the transmitter can quickly detect receiver removal and safely power down the TX coil.

Compensation circuit for compensating for an input charge in a sample and hold circuit

Abstract: A compensation circuit for compensating for an input charge at a first input of a sample and hold circuit, comprising: a first buffer, a first compensation capacitor comprising a first compensation terminal switchable between a first buffer input and a first buffer output, and a second compensation terminal switchable between the first buffer output and a reference terminal, and a control circuit to switch the first compensation terminal to the first buffer output and the second compensation terminal to the reference terminal during sampling, for storing a compensation charge into the first compensation capacitor, and to switch the first compensation terminal to the first buffer input and the second compensation terminal to the first buffer output during holding, for discharging the first compensation capacitor into the first input. The compensation charge is substantially equal to the input charge.

Resistometric Characterization of the Interface between Au Wire Bonds to AlCuW Bond Pads

Abstract: The contact resistance (RC) of Au wires bonded to AlCuW bond pads (98.5% Al, 0.5% Cu, 1.0% W) and pure Al bond pads was measured continuously using the high-resolution resistometric method during multiple high-temperature storage (HTS) tests. Oven storage temperatures from 200°C to 250°C were utilized to accelerate the intermetallic formation and resistance degradation at the bond interface. This study used ceramic side-brazed packages (CERDIPs) with 1 mil Au bond wires ball bonded to the AlCuW bond pads. All devices under test (DUTs) were measured using Kelvin (4-wire) contacts. The mean contact resistance (RC) of an unstressed Au wire ball bond to AlCuW bond pad at room-temperature was 0.186 ohm. The failure time criterion was defined as when the resistance at stress temperature (RT) exceeded 2x (100%) of the initial resistance (R0) but all tests were monitored to a 500% resistance increase. The AlCuW failure distributions show a clear acceleration of the intermetallic degradation mechanism due to increasing temperature. A thermal activation energy was determined using Arrhenius analysis of the median time to failure (t50%) from four different temperatures. A comparison of the contact resistance (RC) intermetallic degradation behavior between the AlCuW and Al bond pad metallurgies is discussed. Scanning Electron Microscope (SEM) images of Focused Ion Bean (FIB) cross-sections confirm that the failure mechanism is due to the formation of intermetallics and subsequently Kirkendall voids. Several Au-Al intermetallic phases were also evident along the Au wire ball bond to Al bond pad interface.

Display control apparatus and method of configuring an interface bandwidth for image data flow

Abstract: A display control apparatus comprising at least one memory element within which image data is stored, at least one display controller arranged to read from the, or each, memory element the image data and to output display data generated from the read image data to at least one display device The display control apparatus further comprises at least one interface component via which the display controller is arranged to read image data from the memory element The display control apparatus further comprises at least one interface bandwidth control component arranged to measure image data flow over the interface component from the memory element to the display controller, and configure a bandwidth for image data flow over the interface component from the memory element to the display controller based at least partly on the measured image data flow

Memory interleave system and method therefor

Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.

Shielded package with integrated antenna

Abstract: A semiconductor structure includes a packaged semiconductor device (100) having at least one device (106,110,104,108), a conductive pillar (112), an encapsulant (202) over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer (802) on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region (604) at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure (1002) over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.

Integrated circuit using standard cells from two or more libraries

Abstract: An integrated circuit (IC) has a block of instances of cells aligned in rows of at least first and second heights. The instances of cells are selected from at least two different libraries of standard cells that have heights that are integer multiples of the first and second heights respectively as a function of performance criteria of the instances of cells. The floorplan provides respective numbers of rows of the different heights as a function of the ratios of the total widths of rows of the different heights needed to place the selected standard cells.

Direct interface between sram and non-volatile memory

Abstract: A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.

Semiconductor device wtih an interconnecting semiconductor electrode between first and second semiconductor electrodes and method of manufacture therefor

Abstract: A semiconductor product comprising: a first semiconductor electrode, a second semiconductor electrode and an interconnecting semiconductor electrode defining a third semiconductor electrode; a first switch, between the first semiconductor electrode and the third semiconductor electrode, provided by a first vertical insulated-gate field-effect-transistor; and a second switch, between the second semiconductor electrode and the third semiconductor electrode, provided by a second vertical insulated-gate field-effect-transistor, wherein the interconnecting semiconductor electrode interconnects the first vertical insulated gate field-effect-transistor and the second vertical insulated gate field-effect-transistor.

Integrated Capacitive Humidity Sensor

Abstract: A semiconductor device composed of a capacitive humidity sensor comprised of a moisture-sensitive polymer layer electrografted to an electrically conductive metal layer situated on an CMOS substrate or a combined MEMS and CMOS substrate, and exposed within an opening through a passivation layer, packages composed of the encapsulated device, and methods of forming the capacitive humidity sensor within the semiconductor device, are provided.

Computing system with a cache invalidation unit, a cache invalidation unit and a method of operating a cache invalidation unit in a computing system

Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.

Sector retirement for split-gate memory

Abstract: A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the control gate driver circuit. And a latch circuit is coupled between the address decoder and the control gate driver circuit. The latch circuit stores a first value, and based on the stored first value, the control gate driver circuit output is floating.