Showing papers by "Freescale Semiconductor published in 2018"

Analog-to-Digital Converter-Based Serial Links: An Overview

Abstract: The ever-increasing number of networked devices and cloud computing applications has created dramatic growth in data center traffic. This necessitates that the serial links that perform the communication between ICs in these systems must operate at higher per-channel data rates, with proposed Ethernet and Optical Internetworking Forum standards supporting 56 Gb/s and scaling beyond 100 Gb/s in the future. However, the large amount of frequency-dependent loss present in conventional electrical channels makes the use of common two-level pulse amplitude modulation (PAM-2) challenging without significant infrastructure upgrades. This motivates the use of the more spectrally efficient four-level PAM (PAM-4). While PAM-4 has a Nyquist frequency half of PAM-2, it is more sensitive to residual intersymbol interference (ISI). Thus, receiver front ends often employ large tap-count feed-forward equalizers (FFEs) that are difficult to robustly implement in the analog domain due to process, voltage, and temperature variations.

Corrosion Mechanisms of Cu Wire Bonding on Al Pads

Abstract: In microelectronic devices, Cu wire bonding on Al-alloy pads suffers from reliability failures that are due to the corrosion of intermetallic compounds (IMC) at the bonding interface. The issue is exacerbated in harsh operation environments with high temperature and high humidity. We studied Cu wire bonding on AlSi bond pads that was packaged and subjected to an un-biased Highly Accelerated Stress Test (uHAST). The most Cu-rich IMC at the bonding interface associated with the failure had been completely corroded, while the least Cu-rich IMC survived. The passivity of the surface oxide of an IMC is compromised likely due to the inherent structural incompatibility between the component aluminum oxide and copper oxide, and consequently the loss of structural integrity of the surface oxide, which makes the IMC less resistant to corrosion than both Al and Cu. The Cu/Al ratio of an IMC decides its ratio of the cathode-to-anode surface areas exposed to the electrolyte, and is expected to be the major factor to determine the corrosion rate of the IMC. The most Cu-rich IMC accordingly exhibits the highest corrosion rate among the IMC; in addition, its interface with the Cu wire has the highest Cu/Al ratio and therefore the highest corrosion rate in the film stack at the bonding interface. Therefore the most Cu-rich IMC is subjected to corrosions along not only the laterally inward direction, but also the vertically downward direction, which exacerbates the preferential corrosion of it. The mechanisms correlate with the widely reported reliability improvements induced by Pd-coating of the wire and other methods. On the outlook to address the reliability issue, both coating of the wire with Ni and replacing Cu wires with Al wires possesses the potential to improve the corrosion resistance, since Ni behaves thermodynamically similar to Pd in the ternary system with Cu and Al, and there will be no IMC formation with the use of Al wires. Both methods, nonetheless, are yet to be verified. To complement, a review of redox reactions generally involved in wire bonding is given, which likewise reveals that the oxidation of an IMC preferentially takes place for the more active element of Al.

Distributed reservation based coherency protocol

Abstract: A method of operating a cache-coherent computing system includes storing first state information corresponding to a first reservation for a first exclusive access to a first memory address requested by a first thread executing on a first processor of a first plurality of processors The method includes transmitting an output atomic response transaction indicating a status of the first reservation to a coherency interconnection in response to issuance of the first exclusive access to the coherency interconnection The output atomic response transaction is based on first state information

Methods and sensor devices for sensing fluid properties

Abstract: An ion sensor for sensing ions in a fluid includes a Metal-Oxide Semiconductor (MOS) varactor formed in and on a semiconductor substrate having a gate dielectric over the semiconductor substrate, a gate over the gate dielectric, a well region in the substrate under the gate dielectric, and source/drain regions in the well region, wherein the well region and the source/drain regions are of a same conductivity type; and a sense electrode coupled to the MOS varactor, wherein the capacitance of the gate dielectric of the varactor changes when the sense electrode interacts with ions in the fluid. Alternatively, resistance of the well region changes when the sense electrode interacts with ions in the fluid, affecting a change in a quality factor of an inductor.

Amplifier architecture reconfiguration

Abstract: An amplifier includes first, second, and third inputs to receive an RF signal, first and second amplifiers, and an input phase adjustment circuit coupling the first, second, and third inputs to the first and second amplifiers, the input phase adjustment circuit having first and second outputs coupled to the first and second amplifiers, respectively. The input phase adjustment circuit includes a pair of inputs, where the pair of inputs includes the first and second inputs, for the first output and a pair of phase adjustment paths coupling the pair of inputs to the first output, respectively. The pair of phase adjustment paths are configured to adjust a phase of the RF signal differently for the first output.

Hardware controlled instruction pre-fetching

Abstract: A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. A load start time is determined for a set of instructions for the particular task. A pre-fetch request is generated to load the set of instructions for the particular task into the memory circuit. The pre-fetch request is forwarded to a hardware loader circuit. In response to the task switch time, a task event trigger is generated for the particular task. The hardware loader circuit is used to load, in response to the pre-fetch request, the set of instructions from a non-volatile memory into the memory circuit.

Multiple interconnections between die

Abstract: Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

Adaptable sense circuitry and method for read-only memory

Abstract: Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.

Transmitter precoding based on quality score

Abstract: A transmitter generates precoding matrices for communication channels of a transmitter, The transmitter includes a plurality of user-specific channels, with each user specific channel associated with a different set of user equipment (UE) receive antennas. For precoding, the transmitter generates a baseline channel matrix reflecting the characteristics of the communication medium employed to transmit data to the different user equipment (UEs). For each user-specific channel, the transmitter generates a set of null space vectors wherein only a subset of the generated null space vectors generated by the transmitter are used to precode the data. To identify the combination of null space vectors to be used for each channel, the transmitter calculates a quality score for each such combination of null space vectors. The transmitter uses the subset of null vectors that yields the highest score to precode the data.

System, test chamber, and method for response time measurement of a pressure sensor

Abstract: A test chamber is used within a system for testing microelectromechanical systems (MEMS) pressure sensors. The system includes a processor, two air tanks pressurized to different air pressures, a high speed switch mechanism, and the test chamber. The test chamber houses a MEMS pressure sensor to be tested, a control pressure sensor, and a temperature sensor. The MEMS pressure sensor and the control pressure sensor are located in a cavity within the test chamber. The cavity is of minimal size and has a domed inner surface. A response time of the MEMS pressure sensor within the cavity can be characterized by utilizing the system and subjecting the MEMS pressure sensor to a pressure stimulus pulse produced by switching between the two air tanks.

Heterogeneous multi-processor device and method of enabling coherent data access within a heterogeneous multi-processor device

Abstract: A heterogeneous multi-processor device having a first processor component arranged to issue a data access command request, a second processor component arranged to execute a set of threads, a task scheduling component arranged to schedule the execution of threads by the second processor component, and an internal memory component. In response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for activities relating to the indicated subset of threads to finish, and when the activities relating to the indicated subset of threads have finished to load a command thread for execution by the second processor component, the command thread being arranged to cause the second processor component to read the indicated data from the at least one region of memory and make the read data available to the first processor component.

Feedback directed program stack optimization

Abstract: A processing device includes an instruction memory to store executable applications that are executable by a target processor, and a compiler. The compiler includes a builder module and a call graph generator. The builder module to build executable applications for the target processor based on a set of instructions. The call graph generator to create a first call graph that indicates a stack usage for each call path of the executable applications. If a first executable application built by the builder module includes a call path that exceeds a stack size constraint of the target processor, the builder module to optimize only functions within the call path that exceeds the stack size constraint in response to the request from the evaluation monitor, and to build a second executable application based on the set of instructions. The second executable application is optimized for stack memory usage of the target processor.

Semiconductor devices and methods for dead time optimization by measuring gate driver response time

Abstract: Switching control devices and related operating methods are provided. An exemplary electronic device includes a semiconductor die, a driver arrangement on the semiconductor die to generate a switch control output signal based on an input switching command signal, and a timer arrangement on the semiconductor die and coupled to the driver arrangement to measure a time difference between a first change in the command signal and an exhibited response in the switch control signal, which can then be utilized to achieve a desired dead time.

Systems and methods for dynamically assigning domain identifiers for access control

Abstract: A master domain assignment controller includes a first plurality of registers corresponding to a first processor including a first register corresponding to a first set of process identifiers (PIDs) and a second register corresponding to a second set of PIDs, and comparison circuitry. The comparison circuitry is coupled to receive an input PID from the first processor and is configured to determine if the input PID is one of the first set or the second set of PIDs. When the input PID is one of the first set of PIDs, a first output domain identifier (DID) is generated, and when the input PID is one of the second set of PIDs, a second output DID different from the first output DID is generated.

Systems and methods of resetting a processor

Abstract: The invention relates to a method of resetting a processor, the method comprising the receiving of a reset signal indicating that one or more parts of said processor need to be reset, and forwarding of said reset signal to said parts to be reset. The forwarding of the reset signal is delayed for a period of time for at least one of the parts to be reset. The clock frequency of at least one of the parts to be reset is gradually decreased during said period of time. In this way the total activity of the processor device is gradually decreased so as to avoid an on-chip voltage overshoot, which could cause a total reset of all the parts of the processor.

On-die signal measurement circuit and method

Abstract: There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

Methods and systems for electrically calibrating transducers

Abstract: Devices, systems and methods are provided for calibrating a transducer. One exemplary method involves determining a transfer function for the transducer based on a measured response of the transducer to an applied electrical signal, determining a set of values for a plurality of response parameters associated with the transducer based on the transfer function, determining a calibration coefficient value associated with the transducer based at least in part on the set of values and a correlation between physical sensitivity and the plurality of response parameters, and storing the calibration coefficient value in association with the transducer.

Aluminum nitride protection of silver apparatus, system and method

Abstract: A semiconductor apparatus including a wafer base with a top side and a bottom side, a silver base with a top side and a bottom side, wherein the bottom side of the silver base is attached to the top side of the wafer base and wherein the silver base provides a reflective surface, and an aluminum nitride protective layer attached to the top side of the silver base, wherein the aluminum nitride protective layer shields the silver base from the environment.

Microelectromechanical systems device test system and method

Abstract: A system includes a rotary platform adapted to undergo oscillatory motion about a fixed point, a test fixture coupled to the rotary platform, the test fixture being adapted to receive a device-under-test, and an inertial sensor mounted to the rotary platform for providing a motion output signal indicative of the oscillatory motion. A controller is in communication with the rotary platform and inertial sensor. The controller receives the motion output signal and provides a drive signal to the rotary platform responsive to the motion output signal. The controller generates the drive signal in response a test profile and the motion output signal provides feedback of actual movement of the rotary platform. The motion output signal is input to the controller to ensure correspondence between the drive signal and the test profile. A multitude of differing validated environmental vibrational stimuli effects can be evaluated via a sense signal from the device.

Package materials monitor and method therefor

Abstract: A stacked monitor structure and method of measuring thicknesses of embedded layers in a build-up substrate is provided. The stacked monitor structure includes a multi-layer substrate having a first shape formed in a first conductive layer of the multi-layer substrate and a second shape formed in a second conductive layer of the multi-layer substrate, a region of the second shape overlapping the first shape. A first dielectric layer is disposed between the first conductive layer and the second conductive layer. A measuring device is configured to measure a thickness of the first conductive layer at a first location on the stacked monitor structure, a thickness of the second conductive layer at a second location on the stacked monitor structure, and a combined thickness of the first conductive layer, the second conductive layer, and the first dielectric layer at a third location on the stacked monitor structure.

Scheduler for layer mapped code words

Abstract: An eNode-B includes PUSH mapping hardware for improved performance. A scheduler schedules first and second code words of first and second respective user devices. A buffer receives and stores first and second identifiers. A de-multiplexer outputs a first code word number based on the first identifier and a second code word number based on the second identifier. A set of completion queues store the first and second code word numbers. A sequence controller generates first and second select signals corresponding to the first and second identifiers. A multiplexer outputs one of the first and second code word numbers based on the select signals, and the scheduler schedules the first and second code words based on the first and second identifiers.

Mutual capacitance sensing circuit with increased sensitivity

Abstract: An electronic device includes mutual capacitance sensing circuitry for a capacitive touch pad. The touch pad has pairs of transmit and receive electrodes. The sensing circuitry intermittently charges and discharges the transmit electrode, and then measures corresponding voltage level changes at the receive electrode. A non-linear voltage-to-current converter is used to detect the voltage level changes, which allows for great sensitivity to mutual capacitance changes.

Power amplifier system with integrated antenna

Abstract: A system with an integrated antenna includes a housing having a first surface and a second surface The second surface of the housing defines a recess A substrate is attached to first surface of the housing, and an amplifying device having an output node is on the substrate An antenna is attached to the second surface of the housing over the recess A conductive element is positioned through at least a portion of the housing The conductive element electrically connects the antenna to the output node of the amplifying device The conductive element is connected to the antenna at an antenna feed point over the recess in the housing

Complementary gallium nitride integrated circuits

Abstract: An embodiment of a complementary GaN integrated circuit includes a GaN layer with a first bandgap A second layer with a second bandgap is formed on the GaN layer, resulting in a 2DEG in a contact region between the GaN layer and the second layer The second layer has a relatively thin portion and a relatively thick portion A third layer is formed over the relatively thick portion of the second layer The third layer has a third bandgap that is different from the second bandgap, resulting in a 2DHG in a contact region between the second layer and the third layer A transistor of a first conductivity type includes the 2DHG, the relatively thick portion of the second layer, and the third layer, and a transistor of a second conductivity type includes the 2DEG and the relatively thin portion of the second layer

Autonomous hardware for application power usage optimization

Abstract: Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry

Interrupt-controlled direct memory access peripheral data transfer

Abstract: An interrupt controlled prefetching and caching technique includes transferring peripheral data from a peripheral to a peripheral cache via direct memory access in response to receiving an interrupt request from the peripheral. The technique includes executing an interrupt service routine prologue in response to completion of transferring of peripheral data. The technique may include providing a base address and a transfer trigger to initiate the transferring of the peripheral data. The technique may include executing a peripheral interrupt service routine after executing the interrupt service routine prologue. The technique may include executing an interrupt service routine epilogue after executing the peripheral interrupt service routine, the interrupt service routine epilogue including resetting an interrupt status flag associated with the interrupt request. Executing the interrupt service routine may include executing instructions using the peripheral data at a rate at least an order of magnitude faster than an access time of the peripheral.