Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Amplifier
Papers published on a yearly basis
Papers
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26 Oct 1987TL;DR: In this article, the TAB (Tape Automated Bonding) process uses single-layer tapes to form a semiconductor structure, and the bottom surface of the chip preferably remains uncovered so that it can be electrically connected to ground or another potential.
Abstract: A TAB (Tape Automated Bonding) process uses single-layer tapes to form a semiconductor structure. Beam leads on a metal tape are "inner-lead bonded" to a chip. Each chip site on a specially-formed plastic tape has a central portion and a peripheral portion which are bonded to the chip so that the central portion forms a protective cover over the chip and the peripheral portion acts as a support for the beam leads during probe testing, excising and forming operations, etc. The bottom surface of the chip preferably remains uncovered so that it can, if appropriate, be electrically connected to ground or another potential.
53 citations
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29 May 2003TL;DR: A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to plurality of masters (12,14), determining access permissions (86), providing state information (60), and selectively modifying the access permissions based on the state information.
Abstract: A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12,14), determining access permissions (86), providing state information (60), determining access permissions (86) based on the access request (84), and selectively modifying the access permissions based on the state information (90). The state information (60) may relate to debug operation, operation from unsecure or unverified memories, memory programming, direct memory access operation, boot operation, software security verification, security levels, security monitor operation, operating mode, fault monitor, external bus interface, etc (88).
53 citations
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02 Oct 2003TL;DR: In this article, an MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell, and methods are provided for reading an MTJ in a ganged memory cell of the MRAM.
Abstract: An MRAM is provided that minimizes the limits in MRAM density imposed by utilization of an isolation or select device in each memory cell. In addition, methods are provided for reading an MTJ in a ganged memory cell of the MRAM. The method includes determining an electrical value that is at least partially associated with a resistance of a ganged memory cell of the MRAM. The MTJ in the ganged memory cell is toggled and a second electrical value, which is at least partially associated with the resistance of the ganged memory cell, is determined after toggling the MTJ. Once the electrical value prior to the toggling and after the toggling is determined, the difference between the two electrical values is analyzed to determine the value of the MTJ.
53 citations
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05 Jan 2009TL;DR: In this article, a system comprises a signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least 1 memory element.
Abstract: A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.
53 citations
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03 Sep 1985TL;DR: In this article, a charge pump which can operate at low supply voltages is provided, which recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices.
Abstract: A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.
53 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |